AMD LX 900@1.5W Benutzerhandbuch
AMD Geode™ LX Processors Data Book
517
Security Block Register Descriptions
33234H
GLD_MSR_ERROR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
RB_ERR
_S
T
A
TUS
RA_ERR
_S
T
A
TUS
RSVD
AES_ERR_ST
A
T
US
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
RB_ERR_MASK
RA_ERR_MASK
RSVD
AES_
ERR_MAS
K
GLD_MSR_Error Bit Descriptions
Bit
Name
Description
63:37
RSVD
Reserved.
36
RB_ERR_
STATUS
STATUS
Response B Error Status. When set, this bit indicates that context B received a
response with either the SSMI or Exception flag set. This can occur on any of the read
responses or on the last write of an encrypt or decrypt operation that also requires a
response. If the error occurs on a read response, the operation is terminated and the
state machine returns to idle and signals completion. Write a one to this bit to clear the
status.
response with either the SSMI or Exception flag set. This can occur on any of the read
responses or on the last write of an encrypt or decrypt operation that also requires a
response. If the error occurs on a read response, the operation is terminated and the
state machine returns to idle and signals completion. Write a one to this bit to clear the
status.
35
RA_ERR_
STATUS
STATUS
Response A Error Status. When set, this bit indicates that context A received a
response with either the SSMI or Exception flag set. This can occur on any of the read
responses or on the last write of an encrypt or decrypt operation that also requires a
response. If the error occurs on a read response, the operation is terminated and the
state machine returns to idle and signals completion. Write a one to this bit to clear the
status.
response with either the SSMI or Exception flag set. This can occur on any of the read
responses or on the last write of an encrypt or decrypt operation that also requires a
response. If the error occurs on a read response, the operation is terminated and the
state machine returns to idle and signals completion. Write a one to this bit to clear the
status.
34-33
RSVD
Reserved.
32
AES_ERR_
STATUS
STATUS
AES Error Status. Reserved Type. This bit is set if the module receives a transaction
identified with a reserved transaction type. This implies a hardware error.
identified with a reserved transaction type. This implies a hardware error.
0: AES Error not pending.
1: AES Error pending.
1: AES Error pending.
Writing a 1 to this bit clears the status.
31:3
RSVD
Reserved.
4
RB_ERR_
MASK
MASK
Response B Error Mask. When set, this bit masks the Response B Error (bit 36) and
prevents generation of the error output. When cleared, the error is enabled and asser-
tion of Response B Error will generate an error.
prevents generation of the error output. When cleared, the error is enabled and asser-
tion of Response B Error will generate an error.
3
RA_ERR_
MASK
MASK
Response A Error Mask. When set, this bit masks the Response A Error (bit 35) and
prevents generation of the error output. When cleared, the error is enabled and asser-
tion of Response A Error will generate an error.
prevents generation of the error output. When cleared, the error is enabled and asser-
tion of Response A Error will generate an error.
2:1
RSVD
Reserved.
0
AES_ERR_
MASK
MASK
AES Error Mask. Reserved Type.
0: Unmask the Error (enabled).
1: Mask the Error (disabled).
1: Mask the Error (disabled).