Texas Instruments TMS320C2XX Benutzerhandbuch
Index
Index-22
synchronous serial port
(continued)
troubleshooting
bits for testing the port
error conditions
burst mode
continuous mode
underflow in transmitter
burst mode
continuous mode
synchronous serial port registers
control register (SSPCR)
description
quick reference
FIFO buffers
detecting data in receive FIFO buffer (RFNE
bit)
detecting empty transmit FIFO buffer (TCOMP
bit)
introduction
managing contents with SDTR
overview
receive shift register (RSR)
transmit and receive register (SDTR)
using to access FIFO buffers
transmit shift register (XSR)
T
target cable
target system, connection to emulator
target system emulator connector, designing
target-system clock
TBLR instruction
TBLW instruction
TC (test/control flag bit)
response to accumulator event
response to auxiliary register compare
TCK signal
TCOMP bit
TCR (timer control register)
’C209
quick reference
TDDR (timer divide-down register)
’C203/C204
’C209
definition
TDI signal
TDO signal
temporary register (TREG)
TEMT bit
test bus controller
test clock
diagram
test/control flag bit (TC)
response to accumulator event
response to auxiliary register compare
THRE bit
TIM (timer counter register)
TIM bit
timer
block diagram
control register (TCR)
counter register (TIM)
divide-down register (TDDR)
’C203/C204
’C209
11-16
definition
emulation modes (FREE and SOFT bits)
interrupt (TINT)
’C203/C204
flag bit
mask bit
priority
vector location
’C209
flag bit
mask bit
priority
vector location
interrupt rate
operation
period register (PRD)
prescaler counter (PSC)
’C203/C204
’C209
11-15
reload
’C203/C204
’C209
11-15
reset
setting interrupt rate
stop/start
’C203/C204
’C209
11-16