Motorola MCPN750A Benutzerhandbuch
2-8
Computer Group Literature Center Web Site
Startup and Operation
2
PCI Arbitration
The MCPN750A has six potential local PCI bus masters:
❏
the Raven ASIC,
❏
the PBC device (VT82C586B),
❏
the Ethernet device (21143),
❏
the PCI-to-PCI bridge device (21554),
❏
and each of the two PMCs.
The local PCI arbiter is implemented in an onboard PLD. This arbiter
implements a rotating priority scheme with equal priorities. Since the PBC
device does not support bus parking, the arbiter will park on the Raven
when the bus is idle.
implements a rotating priority scheme with equal priorities. Since the PBC
device does not support bus parking, the arbiter will park on the Raven
when the bus is idle.
Interrupt Handling
The Raven ASIC provides a Multi-Processor Interrupt Controller (MPIC)
to handle various interrupt sources. This MPIC supports up to two
processors and 16 external interrupt sources. There are also six other
interrupt sources inside the MPIC: Two cross-processor interrupts and four
timer interrupts. All ISA interrupts go through the 8259 pair in the
Peripheral Bus Controller (PBC). The output of the PBC then goes through
the MPIC in Raven.
to handle various interrupt sources. This MPIC supports up to two
processors and 16 external interrupt sources. There are also six other
interrupt sources inside the MPIC: Two cross-processor interrupts and four
timer interrupts. All ISA interrupts go through the 8259 pair in the
Peripheral Bus Controller (PBC). The output of the PBC then goes through
the MPIC in Raven.
Since the MCPN750A board is designed to support processor data bus
parity, the Raven uses some of the pins normally used as external interrupt
inputs as parity pins. Therefore, an Interrupt Multiplexer device,
implemented in a PLD, is used to scan the external MPIC interrupts into
Raven as a serial bit stream using the Raven SISTA and SIDAT pins. This
operation is automatic and transparent to the software. A maximum delay
of 240 nanoseconds should be expected from the time that the external
interrupt is generated and when it is presented to the MPIC. Sources of
interrupts may be any of the following:
parity, the Raven uses some of the pins normally used as external interrupt
inputs as parity pins. Therefore, an Interrupt Multiplexer device,
implemented in a PLD, is used to scan the external MPIC interrupts into
Raven as a serial bit stream using the Raven SISTA and SIDAT pins. This
operation is automatic and transparent to the software. A maximum delay
of 240 nanoseconds should be expected from the time that the external
interrupt is generated and when it is presented to the MPIC. Sources of
interrupts may be any of the following:
❏
The Raven ASIC itself (four MPIC timer interrupts or transfer error
interrupts)
interrupts)