Motorola CPCI-6020 Benutzerhandbuch
CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C)
Functional Description
Dual Harrier Assignments
88
z
Single channel DMA controller
z
Message passing unit supporting I2O and generic functions
z
Two internal 16550-type UARTs
z
Two I
2
C Bus master interfaces
z
MPIC compliant interrupt controller
z
Four Xport channels for interfacing to flash or other external registers/devices
Refer to the Harrier Application Specific Integrated Circuit (ASIC) Programmer’s Reference
Guide (ASICHRA1/PG) for additional information and programming details.
Guide (ASICHRA1/PG) for additional information and programming details.
4.6.1
Dual Harrier Assignments
The CPCI-6020 employs dual Harrier ASICs identified as Harrier A and Harrier B. Harrier A is
used for access to part of system memory, access to all of flash memory, NVRAM, RTC,
external registers, UARTs, onboard I
used for access to part of system memory, access to all of flash memory, NVRAM, RTC,
external registers, UARTs, onboard I
2
C, bridging to PCI Bus A and for top level control of all
interrupts. Harrier B is used for access to part of system memory, bridging to PCI Bus B and for
controlling some interrupts.
controlling some interrupts.
4.6.2
Harrier Power-Up Configuration
The Harrier ASIC XAD30-XAD0 pins provide configuration information for Harrier at power-up
reset time. The following table lists the default power-up reset state of these pins for the CPCI-
6020. The Select Option column indicates whether the power up setting can be changed by
build option resistor or by jumper, or if the setting is fixed and cannot be changed. The default
power-up setting column indicates the default values of the standard CPCI-6020 product.
Default settings for jumper options indicate power up value with jumper not installed.
reset time. The following table lists the default power-up reset state of these pins for the CPCI-
6020. The Select Option column indicates whether the power up setting can be changed by
build option resistor or by jumper, or if the setting is fixed and cannot be changed. The default
power-up setting column indicates the default values of the standard CPCI-6020 product.
Default settings for jumper options indicate power up value with jumper not installed.
Table 4-2 Harrier Power-Up Configuration Settings
Harrier
XAD Bus
Signal
XAD Bus
Signal
Select
Option
Option
Power Up
Default
Default
Register Bit(s)
Meaning of Power-Up
Default State
Default State
XAD[30]
Resistor
0
XCSR.XPGC.HDM
Xports not Hawk Data Mode compatible.
XAD[29]
Fixed
0
XCSR.UCTL.UCOS
Select external clock source for UART.
XAD[28]
Resistor
0
XCSR.BPCS.CSH
Other PCI masters may access Harrier
configuration space.
configuration space.
XAD[27]
Resistor
0
XCSR.BPCS.CSM
All of Harrier’s PCI configuration
registers are visible from PCI space.
registers are visible from PCI space.
XAD[26]
Resistor
0
XCSR.BXCS.P0HO
/P1HO
/P1HO
Disable processor hold off at power up.
XAD[25]
Fixed
1
XCSR.SDTC.SDER
There are external buffers in series with
the BAx, RAx, WE, RAS or CAS signals.
the BAx, RAx, WE, RAS or CAS signals.
XAD[24]
Resistor
A = 1
B = 0
XCSR.GCSR.AOA
O
O
Harrier A will respond to unmapped
address only cycles, Harrier B will not.
address only cycles, Harrier B will not.