Motorola CPCI-6020 Benutzerhandbuch
Harrier B Memory Bus
Functional Description
CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C)
91
4.7.2
Harrier B Memory Bus
Harrier B memory bus is also routed to a RAM500 compatible connector and has capabilities
and characteristics identical to the Harrier A memory bus. The ECC protected memory banks
on this memory bus appear as Banks C and E to Harrier B.
and characteristics identical to the Harrier A memory bus. The ECC protected memory banks
on this memory bus appear as Banks C and E to Harrier B.
4.7.3
RAM500 Memory Mezzanine
Each RAM500 mezzanine carries nine SDRAM parts in a x8 configuration, a buffer for certain
control signals and a single +3.3 V, 256 x 8, SPD serial ROM. Each lower RAM500 attached to
the host board has its SPD addressable at $AA from the Harrier to which it is attached, the
upper at $AC.
control signals and a single +3.3 V, 256 x 8, SPD serial ROM. Each lower RAM500 attached to
the host board has its SPD addressable at $AA from the Harrier to which it is attached, the
upper at $AC.
The following are the expansion mezzanine size options for a single board. Boards of any size
can be stacked.
can be stacked.
4.8
Harrier Xport Resources
The Xport is a bridge that interfaces the 60x bus to an expansion bus named Xport Bus. Each
of the two Harriers on CPCI-6020 has a separate Xport Bus. The Xport Bus is the set of signals
Harrier uses to control devices that have a simple, static RAM style interface. Such devices
include flash, NVRAM, RTC and external registers. A 60x bus slave and an Xport Bus master
constitute the most significant blocks that make up Xport within Harrier. The 60x bus slave has
four address response ranges. The Xport Bus master has four corresponding chip selects. An
address range with its corresponding chip select is referred to as a channel (0 through 3). Each
channel employs a combination of control registers and input signal pins to configure its
address range and attributes. Refer to the Harrier Engineering Specification for additional
details.
of the two Harriers on CPCI-6020 has a separate Xport Bus. The Xport Bus is the set of signals
Harrier uses to control devices that have a simple, static RAM style interface. Such devices
include flash, NVRAM, RTC and external registers. A 60x bus slave and an Xport Bus master
constitute the most significant blocks that make up Xport within Harrier. The 60x bus slave has
four address response ranges. The Xport Bus master has four corresponding chip selects. An
address range with its corresponding chip select is referred to as a channel (0 through 3). Each
channel employs a combination of control registers and input signal pins to configure its
address range and attributes. Refer to the Harrier Engineering Specification for additional
details.
Table 4-3 Expansion SDRAM Memory Mezzanine Size Options
SDRAM Memory
Size (Banks)
Size (Banks)
Device Size
Device Organization
(depth x width-in-bits)
(depth x width-in-bits)
Number
of Banks
of Banks
Number of
Devices
Devices
32 MB
64 megabit
4 MB X 16
1
5
64 MB
64 megabit
8 MB X 8
1
9
128 MB
128 megabit
16 MB X 8
1
9
256 MB
256 megabit
32 MB X 8
1
9
512 MB
512 megabit
64 MB X 8
1
9