Texas Instruments TMS320C645x DSP Benutzerhandbuch
1
Introduction
1.1
Purpose of the Peripheral
1.2
Features
User's Guide
SPRU975B – August 2006
Ethernet Media Access Controller (EMAC)/Management
Data Input/Output (MDIO)
This document provides a functional description of the Ethernet Media Access Controller (EMAC) and
Physical layer (PHY) device Management Data Input/Output (MDIO) module integrated with
TMS320C645x (C645x) devices. Included are the features of the EMAC and MDIO modules, a discussion
of their architecture and operation, how these modules connect to the outside world, and the registers
description for each module.
Physical layer (PHY) device Management Data Input/Output (MDIO) module integrated with
TMS320C645x (C645x) devices. Included are the features of the EMAC and MDIO modules, a discussion
of their architecture and operation, how these modules connect to the outside world, and the registers
description for each module.
The EMAC controls the flow of packet data from the processor to the PHY. The MDIO module controls
PHY configuration and status monitoring.
PHY configuration and status monitoring.
Both the EMAC and the MDIO modules interface to the DSP through a custom interface that allows
efficient data transmission and reception. This custom interface is referred to as the EMAC control
module, and is considered integral to the EMAC/MDIO peripheral.
efficient data transmission and reception. This custom interface is referred to as the EMAC control
module, and is considered integral to the EMAC/MDIO peripheral.
The EMAC module is used on TMS320C645x devices to move data between the device and another host
connected to the same network, in compliance with the Ethernet protocol.
connected to the same network, in compliance with the Ethernet protocol.
The basic feature set of the EMAC module integrated with C645x is:
•
Synchronous 10/100/1000 Mbps operation
•
Full duplex Gigabit operation (half duplex gigabit is not supported)
•
Little endian and big endian support
•
Supports four types of interfaces to the physical layer device (PHY): standard media independent
interface (MII), reduced pin count media independent interface (RMII), standard gigabit media
independent interface (GMII) and reduced pin count gigabit media independent interface (RGMII)
interface (MII), reduced pin count media independent interface (RMII), standard gigabit media
independent interface (GMII) and reduced pin count gigabit media independent interface (RGMII)
•
EMAC acts as DMA master to either internal or external device memory space
•
Eight receive channels with VLAN tag discrimination for receive quality of service (QOS) support
•
Eight transmit channels with round–robin or fixed priority for transmit quality of service (QOS) support
•
Ether-stats and 802.3-stats statistics gathering
•
Transmit CRC generation selectable on a per-channel basis
•
Broadcast frames selection for reception on a single channel
•
Multicast frames selection for reception on a single channel
•
Promiscuous receive mode frames selection for reception on a single channel (all frames, all good
frames, short frames, error frames)
frames, short frames, error frames)
•
Hardware flow control
•
8K byte local EMAC descriptor memory that allows the peripheral to operate on descriptors without
affecting the CPU. The descriptor memory holds enough information to transfer up to 512 ethernet
packets without CPU intervention.
affecting the CPU. The descriptor memory holds enough information to transfer up to 512 ethernet
packets without CPU intervention.
•
Programmable interrupt logic permits the software driver to restrict the generation of back-to-back
interrupts, thus allowing more work to be performed in a single call to the interrupt service routine
interrupts, thus allowing more work to be performed in a single call to the interrupt service routine
SPRU975B – August 2006
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
11