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5.27 Receive Channel 0-7 Flow Control Threshold Register (RXnFLOWTHRESH)
EMAC Port Registers
The receive channel 0-7 flow control threshold register (RXnFLOWTHRESH) is shown in
and
described in
.
Figure 55. Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH)
31
16
Reserved
R-0
15
8
7
0
Reserved
RXnFLOWTHRESH
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 55. Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH) Field
Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
Reserved
7-0
RXnFLOW
Receive flow threshold. These bits contain the threshold value for issuing flow control on incoming
THRESH
frames for channel n (when enabled).
SPRU975B – August 2006
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
111