Texas Instruments TMS320C645x DSP Benutzerhandbuch
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5.40 Transmit Pacing Algorithm Test Register (TPACETEST)
EMAC Port Registers
The Transmit Pacing Algorithm Test Register (TPACETEST) is shown in
and described in
.
Figure 68. Transmit Pacing Algorithm Test Register (TPACETEST)
31
16
Reserved
R-0
15
5
4
0
Reserved
PACEVAL
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 68. Transmit Pacing Algorithm Test Register (TPACETEST) Field Descriptions
Bit
Field
Value
Description
31-5
Reserved
0
Reserved
4-0
PACEVAL
Pacing register current value. A nonzero value in this field indicates that transmit pacing is active. A
transmit frame collision or deferral causes PACEVAL to be loaded with 1Fh (31); good frame
transmissions (with no collisions or deferrals) cause PACEVAL to be decremented down to 0.
When PACEVAL is nonzero, the transmitter delays four Inter Packet Gaps between new frame
transmissions after each successfully transmitted frame that had no deferrals or collisions. If a
transmit frame is deferred or suffers a collision, the IPG time is not stretched to four times the
normal value. Transmit pacing helps reduce capture effects, which improves overall network
bandwidth.
transmit frame collision or deferral causes PACEVAL to be loaded with 1Fh (31); good frame
transmissions (with no collisions or deferrals) cause PACEVAL to be decremented down to 0.
When PACEVAL is nonzero, the transmitter delays four Inter Packet Gaps between new frame
transmissions after each successfully transmitted frame that had no deferrals or collisions. If a
transmit frame is deferred or suffers a collision, the IPG time is not stretched to four times the
normal value. Transmit pacing helps reduce capture effects, which improves overall network
bandwidth.
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
126
SPRU975B – August 2006