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5.49 Receive Channel 0-7 Completion Pointer Register (RXnCP)
EMAC Port Registers
The receive channel 0-7 completion pointer register (RXnCP) is shown in
and described in
.
Figure 77. Receive Channel n Completion Pointer Register (RXnCP)
31
16
RXnCP
R/W-x
15
0
RXnCP
R/W-x
LEGEND: R/W = Read/Write; -n = value after reset
Table 77. Receive Channel n Completion Pointer Register (RXnCP) Field Descriptions
Bit
Field
Value
Description
31-0
RXnCP
Receive channel n completion pointer register is written by the host with the buffer descriptor
address for the last buffer processed by the host during interrupt processing. The EMAC uses the
value written to determine if the interrupt should be de-asserted.
address for the last buffer processed by the host during interrupt processing. The EMAC uses the
value written to determine if the interrupt should be de-asserted.
SPRU975B – August 2006
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
135