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3.3
EMAC Control Module Interrupt Timer Count Register (EWINTTCNT)
EMAC Control Module Registers
The EMAC control module interrupt timer count register (EWINTTCNT) is used to control the generation of
back-to-back interrupts from the EMAC and MDIO modules. The value of this timer count is loaded into an
internal counter every time interrupts are enabled using EWCTL. A second interrupt cannot be generated
until this count reaches 0. The counter is decremented at a frequency of CPU clock/6; its default reset
count is 0 (inactive), its maximum value is 1 FFFFh (131 071).
back-to-back interrupts from the EMAC and MDIO modules. The value of this timer count is loaded into an
internal counter every time interrupts are enabled using EWCTL. A second interrupt cannot be generated
until this count reaches 0. The counter is decremented at a frequency of CPU clock/6; its default reset
count is 0 (inactive), its maximum value is 1 FFFFh (131 071).
The EMAC control module interrupt timer count register (EWINTTCNT) is shown in
and
described in
.
Figure 15. EMAC Control Module Interrupt Timer Count Register (EWINTTCNT)
31
17
16
Reserved
EWINT
TCNT
R-0
R/W-0
15
0
EWINTTCNT
R/W-0
LEGEND: R = Read only; R/W = Read/Write; -n = value after reset
Table 13. EMAC Control Module Interrupt Timer Count Register (EWINTTCNT) Field Descriptions
Bit
Field
Value
Description
31-17
Reserved
0
Reserved
16-0
EWINTTCNT
Interrupt timer count. EWINTTCNT is a 17-bit interrupt timer count that is used to control the
generation of back-to-back interrupts from the EMAC and MDIO modules. The value of
EWINTTCNT is loaded in an internal time counter every time interrupts are enabled using EWCTL
register by writing a '1' to INTEN bit. (Note the INTEN bit must transition from '0' to '1' to initialize
the internal time counter.) Once initialized, the time counter will count down with each peripheral
clock till it reaches zero. A second interrupt cannot be generated until this counter reaches 0. Any
time the time counter has a non-zero value, the interrupt logic will block the EMAC_MDIO_INT
interrupt to the CPU. Thus, if any of the interrupts coming to the EMAC control module is asserted,
the interrupt logic will assert the EMAC_MDIO_INT signal to the CPU, provided the INTEN bit in the
EWCTL register is set, and the time counter value is zero.
generation of back-to-back interrupts from the EMAC and MDIO modules. The value of
EWINTTCNT is loaded in an internal time counter every time interrupts are enabled using EWCTL
register by writing a '1' to INTEN bit. (Note the INTEN bit must transition from '0' to '1' to initialize
the internal time counter.) Once initialized, the time counter will count down with each peripheral
clock till it reaches zero. A second interrupt cannot be generated until this counter reaches 0. Any
time the time counter has a non-zero value, the interrupt logic will block the EMAC_MDIO_INT
interrupt to the CPU. Thus, if any of the interrupts coming to the EMAC control module is asserted,
the interrupt logic will assert the EMAC_MDIO_INT signal to the CPU, provided the INTEN bit in the
EWCTL register is set, and the time counter value is zero.
SPRU975B – August 2006
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
65