Texas Instruments TMS320C645x DSP Benutzerhandbuch
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5.9
Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED)
EMAC Port Registers
The transmit interrupt status (Masked) register (TXINTSTATMASKED) is shown in
and
described in
.
Figure 37. Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED)
31
16
Reserved
R-0
15
8
7
6
5
4
3
2
1
0
Reserved
TX7
TX6
TX5
TX4
TX3
TX2
TX1
TX0
PEND
PEND
PEND
PEND
PEND
PEND
PEND
PEND
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R/W = R = Read only; -n = value after reset
Table 37. Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
Reserved
7
TX7PEND
TX7PEND masked interrupt read
6
TX6PEND
TX6PEND masked interrupt read
5
TX5PEND
TX5PEND masked interrupt read
4
TX4PEND
TX4PEND masked interrupt read
3
TX3PEND
TX3PEND masked interrupt read
2
TX2PEND
TX2PEND masked interrupt read
1
TX1PEND
TX1PEND masked interrupt read
0
TX0PEND
TX0PEND masked interrupt read
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
92
SPRU975B – August 2006