Texas Instruments SPRU938B Benutzerhandbuch
www.ti.com
2.10 Reset Considerations
2.10.1
Software Reset Considerations
2.10.2
Hardware Reset Considerations
2.11 Interrupt Support
2.11.1
Interrupt Events and Requests
Peripheral Architecture
Peripheral clock and reset control is done through the power and sleep controller (PSC) module that is
included with the device. For more information, see
included with the device. For more information, see
. Additionally, there is a software reset
(the reset bit in the VLYNQ control register, CTRL) within the peripheral itself. Writing a 1 to the reset bit
resets all of the internal state machines of the VLYNQ module, the serial interface is disabled, and the link
is lost. The VLYNQ module remains in reset until the software clears the bit.
resets all of the internal state machines of the VLYNQ module, the serial interface is disabled, and the link
is lost. The VLYNQ module remains in reset until the software clears the bit.
Note:
When setting the reset bit, the VLYNQ status register (STAT) value is the only value that is
set to the default value. All of the other VLYNQ memory-mapped registers retain their values
prior to the software reset.
set to the default value. All of the other VLYNQ memory-mapped registers retain their values
prior to the software reset.
When a hardware reset occurs, the VLYNQ peripheral resets its register values to the default values and
the serial interface is disabled. After a hardware reset, the VLYNQ memory mapped registers and any
chip-level registers that are associated with VLYNQ (for example, pin multiplexing registers) must be
configured appropriately before data transmission can resume.
the serial interface is disabled. After a hardware reset, the VLYNQ memory mapped registers and any
chip-level registers that are associated with VLYNQ (for example, pin multiplexing registers) must be
configured appropriately before data transmission can resume.
CAUTION
Be cautious when only resetting one of the VLYNQ devices after two or more
VLYNQ devices have established a link. If only one of the VLYNQ devices is in
reset, then no data activity can occur across the serial interface during the time
of reset.
VLYNQ devices have established a link. If only one of the VLYNQ devices is in
reset, then no data activity can occur across the serial interface during the time
of reset.
The VLYNQ module interrupt VLQINT is mapped to the interrupt controller (INT55). For more information
on the interrupt controller, see the device-specific data manual.
on the interrupt controller, see the device-specific data manual.
Interrupts generate when bits are set in the VLYNQ interrupt pending/set register (INTPENDSET). Bits are
set in the INTPENDSET register when any of the following occur:
set in the INTPENDSET register when any of the following occur:
•
Writing directly to the INTPENDSET
•
Remote interrupt (via the serial interrupt packet)
•
Serial bus error
When INTPENDSET is a non-zero value, the method of forwarding the interrupt status depends on the
state of the INTLOCAL bit in the VLYNQ control register (CTRL):
state of the INTLOCAL bit in the VLYNQ control register (CTRL):
•
When INTLOCAL = 0, the contents of INTPENDSET are inserted into an interrupt packet and sent
over the serial interface. When packet transmission completes, the associated bits clear in
INTPENDSET.
over the serial interface. When packet transmission completes, the associated bits clear in
INTPENDSET.
•
When INTLOCAL = 1, bits in INTPENDSET transfer to the VLYNQ interrupt status/clear register
(INTSTATCLR). The logical-OR of all of the bits in INTSTATCLR is driven onto the interrupt line,
causing the VLYNQINT to pulse. If the system writes to INTSTATCLR while interrupts are still pending,
a new VLQINT interrupt is generated.
(INTSTATCLR). The logical-OR of all of the bits in INTSTATCLR is driven onto the interrupt line,
causing the VLYNQINT to pulse. If the system writes to INTSTATCLR while interrupts are still pending,
a new VLQINT interrupt is generated.
20
VLYNQ Port
SPRU938B – September 2007