Texas Instruments TMS320TCI648x Benutzerhandbuch
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5.4
Peripheral Settings Control Register (PER_SET_CNTL)
SRIO Registers
The peripheral settings control register (PER_SET_CNTL) is shown in
and described in
. For additional programming information, see
Figure 65. Peripheral Settings Control Register (PER_SET_CNTL) (Address Offset 0020h)
31
27
26
25
24
SW_MEM_SLEEP_
BOOT_
Reserved
LOOPBACK
OVERRIDE
COMPLETE
R-0
R/W-1
R/W-0
R/W-0
23
21 20
18 17
16
Reserved
TX_PRI2_WM
TX_PRI1_WM
R-0
R/W-01h
R/W-02h
15
14
12 11
9
8
TX_PRI1_WM
TX_PRI0_WM
CBA_TRANS_PRI
1X_MODE
R/W-02h
R/W-03h
R/W-0
R/W-0
7
4
3
2
1
0
PRESCALER_SELECT
ENPLL4
ENPLL3
ENPLL2
ENPLL1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 43. Peripheral Settings Control Register (PER_SET_CNTL) Field Descriptions
Bit
Field
Value
Description
31–27
Reserved
00000b
These read-only bits return 0s when read.
26
SW_MEM_SLEEP_OVERRIDE
Software memory sleep override
0
Memories are put in sleep mode while in shutdown
1
Memories are not put in sleep mode while in shutdown
25
LOOPBACK
Loopback mode
0
Normal operation
1
Loop back mode. Transmit data to receive on the same port. Packet
data is looped back in the digital domain before the SERDES macros.
data is looped back in the digital domain before the SERDES macros.
24
BOOT_COMPLETE
Controls ability to write any register during initialization. It also includes
read only registers during normal mode of operation that have
application defined reset value.
read only registers during normal mode of operation that have
application defined reset value.
0
Write to read-only registers enabled
1
Write to read-only registers disabled. Usually the boot_complete is
asserted once after reset to define power on configuration.
asserted once after reset to define power on configuration.
23–21
Reserved
000b
These read-only bits return 0s when read.
20–18
TX_PRI2_WM
000b–111b
Transmit credit threshold. Sets the required number of logical layer TX
buffers needed to send priority 2 packets across the UDI. This is valid
for all ports in 1x mode only.
Required buffer count for transmit credit threshold 2 value
(TX_PRI2_WM):
buffers needed to send priority 2 packets across the UDI. This is valid
for all ports in 1x mode only.
Required buffer count for transmit credit threshold 2 value
(TX_PRI2_WM):
•
000
→
8, 7, 6, 5, 4, 3, 2, 1 (effectively lets all of this priority pass)
•
001
→
8, 7, 6, 5, 4, 3, 2
•
010
→
8, 7, 6, 5, 4, 3
•
011
→
8, 7, 6, 5, 4
•
100
→
8, 7, 6, 5
•
101
→
8, 7, 6
•
110
→
8, 7
•
111
→
8
SPRUE13A – September 2006
Serial RapidIO (SRIO)
113