Texas Instruments TMS320TCI648x Benutzerhandbuch
1
Overview
1.1
General RapidIO System
1.1.1
RapidIO Architectural Hierarchy
User's Guide
SPRUE13A – September 2006
Serial RapidIO (SRIO)
The RapidIO peripheral used in the TMS320TCI648x is called a serial RapidIO (SRIO). This chapter
describes the general operation of a RapidIO system, how this module is connected to the outside world,
the definitions of terms used within this document, and the features supported and not supported for
SRIO.
describes the general operation of a RapidIO system, how this module is connected to the outside world,
the definitions of terms used within this document, and the features supported and not supported for
SRIO.
RapidIO
®
is a non-proprietary high-bandwidth system level interconnect. It is a packet-switched
interconnect intended primarily as an intra-system interface for chip-to-chip and board-to-board
communications at Gigabyte-per-second performance levels. Uses for the architecture can be found in
connected microprocessors, memory, and memory mapped I/O devices that operate in networking
equipment, memory subsystems, and general purpose computing. Principle features of RapidIO include:
communications at Gigabyte-per-second performance levels. Uses for the architecture can be found in
connected microprocessors, memory, and memory mapped I/O devices that operate in networking
equipment, memory subsystems, and general purpose computing. Principle features of RapidIO include:
•
Flexible system architecture allowing peer-to-peer communication
•
Robust communication with error detection features
•
Frequency and port width scalability
•
Operation that is not software intensive
•
High bandwidth interconnect with low overhead
•
Low pin count
•
Low power
•
Low latency
RapidIO is defined as a 3-layer architectural hierarchy.
•
Logical layer: Specifies the protocols, including packet formats, which are needed by endpoints to
process transactions
process transactions
•
Transport layer: Defines addressing schemes to correctly route information packets within a system
•
Physical layer: Contains the device level interface information such as the electrical characteristics,
error management data, and basic flow control data
error management data, and basic flow control data
In the RapidIO architecture, a single specification for the transport layer is compatible with differing
specifications for the logical and physical layers (see
specifications for the logical and physical layers (see
16
Serial RapidIO (SRIO)
SPRUE13A – September 2006