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5.48 Receive CPPI Control Register (RX_CPPI_CNTL)
SRIO Registers
Each bit in this register indicates whether the associated RX buffer descriptor queue must receive
messages in the order the source device attempts to transmit them. RX_CPPI_CNTL is shown in and
described in
messages in the order the source device attempts to transmit them. RX_CPPI_CNTL is shown in and
described in
. For additional programming information, see
.
Figure 111. Receive CPPI Control Register (RX_CPPI_CNTL) (Address Offset 0744h)
31
24
Reserved
R-00h
23
16
Reserved
R-00h
15
14
13
12
11
10
9
8
QUEUE15_
QUEUE14_
QUEUE13_
QUEUE12_
QUEUE11_
QUEUE10_
QUEUE9_
QUEUE8_
IN_ORDER
IN_ORDER
IN_ORDER
IN_ORDER
IN_ORDER
IN_ORDER
IN_ORDER
IN_ORDER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
QUEUE7_
QUEUE6_
QUEUE5_
QUEUE4_
QUEUE3_
QUEUE2_
QUEUE1_
QUEUE0_
IN_ORDER
IN_ORDER
IN_ORDER
IN_ORDER
IN_ORDER
IN_ORDER
IN_ORDER
IN_ORDER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 116. Receive CPPI Control Register (RX_CPPI_CNTL) Field Descriptions
Bit
Field
Value
Description
31–16
Reserved
0000h
Reserved
15–0
QUEUEn_IN_ORDER
Queuen in order
(n = 15 to 0)
0
Allows out-of-order message reception
1
Requires in-order message reception. Used for applications with
dedicated source-destination flows.
dedicated source-destination flows.
SPRUE13A – September 2006
Serial RapidIO (SRIO)
173