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5.59 Processing Element Logical Layer Control CSR (PE_LL_CTL)
SRIO Registers
The processing element logical layer control CSR (PE_LL_CTL) is shown in
and described in
Figure 122. Processing Element Logical Layer Control CSR (PE_LL_CTL) - Address Offset 104Ch
31
16
Reserved
R-0
15
3 2
0
EXTENDED_
Reserved
ADDRESSING_
CONTROL
R-0
R/W-001
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 130. Processing Element Logical Layer Control CSR (PE_LL_CTL) Field Descriptions
Bit
Field
Value
Description
31–3
Reserved
0
These read-only bits return 0s when read.
2–0
EXTENDED_ADDRESSING_CONTROL
Controls the number of address bits generated by the PE as a
source and processed by the PE as the target of an operation. All
other encodings reserved.
source and processed by the PE as the target of an operation. All
other encodings reserved.
001b
PE supports 34 bit addresses
010b
PE supports 50 bit addresses
100b
PE supports 66 bit addresses
Other
Reserved
Serial RapidIO (SRIO)
190
SPRUE13A – September 2006