Texas Instruments TMS320TCI648x Benutzerhandbuch
Contents
1
Overview
1.1
General RapidIO System
1.2
RapidIO Feature Support in SRIO
1.3
1.4
External Devices Requirements
1.5
TI Devices Supported By This Document
2
SRIO Functional Description
2.1
2.2
SRIO Pins
2.3
Functional Operation
3
Logical/Transport Error Handling and Logging
4
Interrupt Conditions
4.1
CPU Interrupts
4.2
General Description
4.3
Interrupt Condition Status and Clear Registers
4.4
Interrupt Condition Routing Registers
4.5
Interrupt Status Decode Registers
4.6
Interrupt Generation
4.7
Interrupt Pacing
4.8
Interrupt Handling
5
SRIO Registers
5.1
Introduction
....................................................................................................
5.2
Peripheral Identification Register (PID)
5.3
Peripheral Control Register (PCR)
5.4
Peripheral Settings Control Register (PER_SET_CNTL)
5.5
Peripheral Global Enable Register (GBL_EN)
5.6
Peripheral Global Enable Status Register (GBL_EN_STAT)
5.7
Block n Enable Register (BLKn_EN)
5.8
Block n Enable Status Register (BLKn_EN_STAT)
5.9
RapidIO DEVICEID1 Register (DEVICEID_REG1)
5.10
RapidIO DEVICEID2 Register (DEVICEID_REG2)
5.11
Packet Forwarding Register n for 16-Bit Device IDs (PF_16B_CNTLn)
5.12
Packet Forwarding Register n for 8-Bit Device IDs (PF_8B_CNTLn)
5.13
SERDES Receive Channel Configuration Register n (SERDES_CFGRXn_CNTL)
5.14
SERDES Transmit Channel Configuration Register n (SERDES_CFGTXn_CNTL)
5.15
SERDES Macro Configuration Register n (SERDES_CFGn_CNTL)
5.16
DOORBELLn Interrupt Condition Status Register (DOORBELLn_ICSR)
5.17
DOORBELLn Interrupt Condition Clear Register (DOORBELLn_ICCR)
5.18
RX CPPI Interrupt Status Register (RX_CPPI_ICSR)
5.19
RX CPPI Interrupt Clear Register (RX_CPPI_ICCR)
5.20
TX CPPI Interrupt Status Register (TX_CPPI_ICSR)
5.21
TX CPPI Interrupt Clear Register (TX_CPPI_ICCR)
5.22
LSU Interrupt Condition Status Register (LSU_ICSR)
SPRUE13A – September 2006
Table of Contents
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