Freescale Semiconductor MCF52210 Benutzerhandbuch
General Purpose Timer Module (GPT)
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
21-18
Freescale Semiconductor
21.7.4
Pulse Accumulator
The pulse accumulator (PA) is a 16-bit counter that can operate in two modes:
1. Event counter mode: counts edges of selected polarity on the pulse accumulator input pin, PAI
2. Gated time accumulation mode: counts pulses from a divide-by-64 clock
The PA mode bit (PAMOD) selects the mode of operation.
The minimum pulse width for the PAI input is greater than two module clocks.
21.7.5
Event Counter Mode
Clearing the PAMOD bit configures the PA for event counter operation. An active edge on the PAI pin
increments the PA. The PA edge bit (PEDGE) selects falling edges or rising edges to increment the PA.
increments the PA. The PA edge bit (PEDGE) selects falling edges or rising edges to increment the PA.
An active edge on the PAI pin sets the PA input flag (PAIF). The PA input interrupt enable bit (PAI) enables
the PAIF flag to generate interrupt requests.
the PAIF flag to generate interrupt requests.
NOTE
The PAI input and GPT channel 3 use the same pin. To use the PAI input,
disconnect it from the output logic by clearing the channel 3 output mode
and output level bits, OM3 and OL3. Also clear the channel 3 output
compare 3 mask bit (OC3M3).
disconnect it from the output logic by clearing the channel 3 output mode
and output level bits, OM3 and OL3. Also clear the channel 3 output
compare 3 mask bit (OC3M3).
The PA counter register (GPTPACNT) reflects the number of active input edges on the PAI pin since the
last reset.
last reset.
The PA overflow flag (PAOVF) is set when the PA rolls over from 0xFFFF to 0x0000. The PA overflow
interrupt enable bit (PAOVI) enables the PAOVF flag to generate interrupt requests.
interrupt enable bit (PAOVI) enables the PAOVF flag to generate interrupt requests.
NOTE
The PA can operate in event counter mode even when the GPT enable bit
(GPTEN) is clear.
(GPTEN) is clear.
21.7.6
Gated Time Accumulation Mode
Setting the PAMOD bit configures the PA for gated time accumulation operation. An active level on the
PAI pin enables a divide-by-64 clock to drive the PA. The PA edge bit (PEDGE) selects low levels or high
levels to enable the divide-by-64 clock.
PAI pin enables a divide-by-64 clock to drive the PA. The PA edge bit (PEDGE) selects low levels or high
levels to enable the divide-by-64 clock.
The trailing edge of the active level at the PAI pin sets the PA input flag (PAIF). The PA input interrupt
enable bit (PAI) enables the PAIF flag to generate interrupt requests.
enable bit (PAI) enables the PAIF flag to generate interrupt requests.
NOTE
The PAI input and GPT channel 3 use the same pin. To use the PAI input,
disconnect it from the output logic by clearing the channel 3 output mode
(OM3) and output level (OL3) bits. Also clear the channel 3 output compare
mask bit (OC3M3).
disconnect it from the output logic by clearing the channel 3 output mode
(OM3) and output level (OL3) bits. Also clear the channel 3 output compare
mask bit (OC3M3).