Jameco Electronics 3000 Benutzerhandbuch
102
Rabbit 3000 Microprocessor
Serial Port A is selected for bootstrap operation as a clocked serial port when SMODE =
10. In this case bit 7 of Parallel Port C is used for the serial data and bit 1 of Parallel Port B
is used for the serial clock. Note that the serial clock must be externally supplied for boot-
strap operation. This precludes the use of a serial EEPROM for bootstrap operation.
10. In this case bit 7 of Parallel Port C is used for the serial data and bit 1 of Parallel Port B
is used for the serial clock. Note that the serial clock must be externally supplied for boot-
strap operation. This precludes the use of a serial EEPROM for bootstrap operation.
Serial Port A is selected for bootstrap operation as an asynchronous serial port when
SMODE = 11. In this case bit 7 of Parallel Port C is used for the serial data, and the
32 kHz oscillator is used to provide the serial clock. A dedicated divide circuit allows the
use of the 32 kHz signal to provide the timing reference for the 2400 bps asynchronous
transfer. Only 2400 bps is supported for bootstrap operation, and the serial data must be
eight bits for proper operation. In the case of asynchronous bootstrap, Serial Port A
accepts either regular NRZ data or IrDA-encoded data (RZI coding with 3/16ths bit cell)
automatically. The hardware contians a monostable multivibrator triggered by the falling
edge of serial data into the data path. The one shot stretches any IrDA-encoded pulses
enough to look like NRZ data, but not so much as to interfere with real NRZ data.
SMODE = 11. In this case bit 7 of Parallel Port C is used for the serial data, and the
32 kHz oscillator is used to provide the serial clock. A dedicated divide circuit allows the
use of the 32 kHz signal to provide the timing reference for the 2400 bps asynchronous
transfer. Only 2400 bps is supported for bootstrap operation, and the serial data must be
eight bits for proper operation. In the case of asynchronous bootstrap, Serial Port A
accepts either regular NRZ data or IrDA-encoded data (RZI coding with 3/16ths bit cell)
automatically. The hardware contians a monostable multivibrator triggered by the falling
edge of serial data into the data path. The one shot stretches any IrDA-encoded pulses
enough to look like NRZ data, but not so much as to interfere with real NRZ data.
When a bootstrap is performed using Serial Port A, the TXA signal is not needed since the
bootstrap is a one-way communication. After the reset ends and the bootstrap mode
begins, TXA will be low, reflecting its function as a parallel port output bit that is cleared
by the reset. This may be interpreted as a break signal by some serial communication
devices. TXA can be forced high by sending the triplet 0x80, 0x50, 0x40, which stores
0x40 in Parallel Port C. An alternate approach is to send the triplet 0x80, 0x55, 0x40,
which will enable the TXA output from bit 6 of Parallel Port C by writing to the Parallel
Port C function register (0x55).
bootstrap is a one-way communication. After the reset ends and the bootstrap mode
begins, TXA will be low, reflecting its function as a parallel port output bit that is cleared
by the reset. This may be interpreted as a break signal by some serial communication
devices. TXA can be forced high by sending the triplet 0x80, 0x50, 0x40, which stores
0x40 in Parallel Port C. An alternate approach is to send the triplet 0x80, 0x55, 0x40,
which will enable the TXA output from bit 6 of Parallel Port C by writing to the Parallel
Port C function register (0x55).
The transfer rate in any bootstrap operation must not be too fast for the processor to exe-
cute the instruction stream. The Write Empty signal acts as an interlock when using the
Slave Port for bootstrap operation, because the next byte should not be written to the Slave
Port until the Write Empty signal is active. No such interlock exists for the clocked serial
and asynchronous bootstrap operation. In these cases, remember that the processor clock
starts out in divide-by-eight mode with four wait states, and limit the transfer rate accord-
ingly. In asynchronous mode at 2400 bps it takes about 4 ms to send each character, so no
problem is likely unless the system clock is extremely slow.
cute the instruction stream. The Write Empty signal acts as an interlock when using the
Slave Port for bootstrap operation, because the next byte should not be written to the Slave
Port until the Write Empty signal is active. No such interlock exists for the clocked serial
and asynchronous bootstrap operation. In these cases, remember that the processor clock
starts out in divide-by-eight mode with four wait states, and limit the transfer rate accord-
ingly. In asynchronous mode at 2400 bps it takes about 4 ms to send each character, so no
problem is likely unless the system clock is extremely slow.