Jameco Electronics 2000 Benutzerhandbuch
User’s Manual
199
13. R
ABBIT
S
LAVE
P
ORT
When a Rabbit microprocessor is configured as a slave, Parallel Port A and certain other
data lines are used as communication lines between the slave and the master. The slave
unit is a Rabbit configured as a slave. The master can be another Rabbit or any other type
of processor. Rabbits configured as slaves can themselves have slaves.
data lines are used as communication lines between the slave and the master. The slave
unit is a Rabbit configured as a slave. The master can be another Rabbit or any other type
of processor. Rabbits configured as slaves can themselves have slaves.
The master and slave communicate with each other via the slave port. The slave port is a
physical device that includes data registers, a data bus and various handshaking lines. The
slave port is a part of the slave Rabbit, but logically it is an independent device that is used
to communicate between the two processors. A diagram of the slave port is shown in
Figure 13-1.
physical device that includes data registers, a data bus and various handshaking lines. The
slave port is a part of the slave Rabbit, but logically it is an independent device that is used
to communicate between the two processors. A diagram of the slave port is shown in
Figure 13-1.
Figure 13-1. Rabbit Slave Port
The slave port has three data registers for each direction of communication. Three regis-
ters, named SPD0R, SPD1R, and SPD2R, can be written by the master and read by the
slave. Three different registers, also named SPD0R, SPD1R, and SPD2R, can be written
by the slave and read by the master. The same names are used for different registers since
it is usually clear from the context which register is meant. If it is necessary to distinguish
between registers, we will refer to the registers as “SPD0R writable by the slave” or
“SPD0R writable by the master.”
ters, named SPD0R, SPD1R, and SPD2R, can be written by the master and read by the
slave. Three different registers, also named SPD0R, SPD1R, and SPD2R, can be written
by the slave and read by the master. The same names are used for different registers since
it is usually clear from the context which register is meant. If it is necessary to distinguish
between registers, we will refer to the registers as “SPD0R writable by the slave” or
“SPD0R writable by the master.”
SD0-SD7
SA0
SA1
/SWR
/SRD
/SCS
/SLAVEATTN
CPU
SPD0R
SPD1R
SPD2R
SPSR
100
81-88
98
97
95
96
21