Intel 82540EP/EM Benutzerhandbuch

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Flow control capability must be negotiated between link partners via the Auto-Negotiation process. 
The Auto-Negotiation process can modify the value of these bits based on the resolved capability 
between the local device and the link partner.

Once the receiver has validated the reception of an XOFF, or PAUSE frame, the Ethernet controller 
performs the following:

•

Increment the appropriate statistics register(s)

•

Set the TXOFF bit in the Device Status Register (STATUS)

•

Initialize the pause timer based on the packet’s PAUSE timer field

•

Disable packet transmission or schedule the disabling of transmission after the current packet 
completes.

Resumption of transmission can occur under the following conditions:

•

Expiration of the PAUSE timer

•

Reception of on XON frame (a frame with its PAUSE timer set to 0b)

Either condition clears the STATUS.TXOFF bit and transmission can resume. Hardware records 
the number of received XON frames in the XONRXC counter.

When receive flow control is enabled (CTRL.RFCE) is 1b, the following special filtering is 
performed on PAUSE and MAC Control frames.  When receive flow control is disabled, these 
frames are filtered like any other frames and the rest of this section can be ignored.

Two bits in the Receive Control register (RCTL) are implemented specifically for control over 
receipt of PAUSE and MAC control frames. These bits are Discard PAUSE Frames (DPF) and Pass 
MAC Control Frames (PMCF). See 

 for DPF and PMCF bit definitions.

The DPF bit forces the discarding of any valid PAUSE frame addressed to the Ethernet controller’s 
station address. If the packet is a valid PAUSE frame and is addressed to the station address 
(receive address [0]), the Ethernet controller does not pass the packet to host memory if the DPF bit 
is set to logic high. The DPF bit does not affect pause frames that are addressed to the MAC control 
frame multicast address  (01-80-C2-00-00-01).  These frames are DMA’ed if they pass standard 
address filtering, including receive address 1 to 15, multicast hash filtering, or the Multicast 
Promiscuous

 bit is enabled. TheDPF has no affect on PAUSE operation, only the DMA function.

The PMCF bit allows for the passing of any valid MAC control frames to the system which do not 
have a valid PAUSE opcode. In other words, the frame can have the correct MAC control frame 
multicast address (or the MAC station address) as well as the correct type field match with the FCT 
register, but does not have the defined PAUSE opcode of 0001h. Frames of this type are transferred 
to host memory when PMCF is logic high. The results of this filter are logically ORed into the 
standard filters, so even if PMCF is 0b, any MAC control frame that isn't a PAUSE frame that 
passes standard address filtering is DMA’ed