Freescale Semiconductor SC140 Benutzerhandbuch

EOnCE Register Addressing

SC140 DSP Core Reference Manual

4-31

Table 4-12 displays the EOnCE register addressing offsets.

00

R

32

64

ESR

EOnCE status register

01

R/W

32

64

EMCR

Monitor and control register

02

R

64

64

ERCV

EOnCE receive register - least significant 
part

03

R

EOnCE receive register - most significant 
part

04

W

64

64

ETRSMT

EOnCE transmit register - least 
significant part

05

W

EOnCE transmit register - most 
significant part

06

R/W

16

64

EE_CTRL

EE signals control register

07

R

32

32

PC_EXCP

PC of VLES causing Illegal or Overflow 
exception

08

NO

32

32

PC_NEXT

PC of next execution set 

09

NO

32

32

PC_LAST

PC of last execution set

0A

R

32

32

PC_DETECT

PC breakpoint detection register

..........

..........

Reserved addresses

..........

10

R/W

16

32

EDCA0_CTRL

EDCA0 control register

11

R/W

16

32

EDCA1_CTRL

EDCA1 control register

12

R/W

16

32

EDCA2_CTRL

EDCA2 control register

13

R/W

16

32

EDCA3_CTRL

EDCA3 control register

14

R/W

16

32

EDCA4_CTRL

EDCA4 control register

15

R/W

16

32

EDCA5_CTRL

EDCA5 control register

16

Reserved address

17

Reserved address

18

R/W

32

32

EDCA0_REFA

EDCA0 reference value A

19

R/W

32

32

EDCA1_REFA

EDCA1 reference value A

1A

R/W

32

32

EDCA2_REFA

EDCA2 reference value A

1B

R/W

32

32

EDCA3_REFA

EDCA3 reference value A