Texas Instruments TMS320C6457 Benutzerhandbuch
Preface
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1
Introduction to the HPI
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1.1
Summary of the HPI Registers
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1.2
Summary of the HPI Signals
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2
Using the Address Registers
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2.1
Single-HPIA Mode
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2.2
Dual-HPIA Mode
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3
HPI Operation
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3.1
Host-HPI Signal Connections
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3.2
HPI Configuration and Data Flow
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3.3
HDS2, HDS1, and HCS: Data Strobing and Chip Selection
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3.4
HCNTL[1:0] and HR/W: Indicating the Cycle Type
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3.5
HHWIL: Identifying the First and Second Halfwords in 16-Bit Multiplexed Mode
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3.6
HAS: Forcing the HPI to Latch Control Information Early
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3.7
Performing a Multiplexed Access Without HAS
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3.8
Single-Halfword HPIC Cycle in the 16-Bit Multiplexed Mode
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3.9
Hardware Handshaking Using the HPI-Ready (HRDY) Signal
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4
Software Handshaking Using the HPI Ready (HRDY) Bit
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4.1
Polling the HRDY Bit
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5
Interrupts Between the Host and the CPU
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5.1
DSPINT Bit: Host-to-CPU Interrupts
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5.2
HINT Bit: CPU-to-Host Interrupts
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6
FIFOs and Bursting
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6.1
Read Bursting
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6.2
Write Bursting
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6.3
FIFO Flush Conditions
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6.4
FIFO Behavior When a Hardware Reset or Software Reset Occurs
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7
Emulation and Reset Considerations
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7.1
Emulation Modes
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7.2
Software Reset Considerations
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7.3
Hardware Reset Considerations
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8
HPI Registers
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8.1
Introduction
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8.2
Power and Emulation Management Register (PWREMU_MGMT)
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8.3
Host Port Interface Control Register (HPIC)
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8.4
Host Port Interface Address Registers (HPIAW and HPIAR)
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8.5
Data Register (HPID)
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Appendix A Revision History
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3
SPRUGK7A – March 2009 – Revised July 2010
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