Intel 820E Benutzerhandbuch

100  

Design 

Guide 

• 

All RTC OSC signals (RTCX1, RTCX2, VBIAS) should be routed with trace lengths of less than 1 
inch. The shorter, the better. 

• 

Minimize the capacitance between RTCX1 and RTCX2 in the routing. (Optimally, there would be a 
ground line between them.) 

• 

Put a ground plane under all external RTC circuitry. 

• 

Do not route any switching signals under the external components (unless on the other side of the 
ground plane). 

• 

The steady-state VBIAS is a DC voltage of approximately 0.38 V ± 0.06 V. 

• 

When the battery is inserted, the VBIAS is “kicked” to approximately 0.7 V–1.0 V, but it will return 
to its DC value within a few ms. 

• 

Noise on VBIAS must be minimized at 

≤

200 mV. 

• 

VBIAS is very sensitive and cannot be probed directly. It can be probed through a 0.01 µF 
capacitor. 

• 

Excess noise on VBIAS can cause the ICH2 internal oscillator to misbehave or even stop 
completely. 

• 

To minimize VBIAS noise, it is necessary to implement the routing guidelines described previously 
and the required external RTC circuitry. 

All RTC-well inputs (RSMRST#, RTCRST#, INTRUDER#) must be either pulled up to VCCRTC or 
pulled down to ground while in G3 state. RTCRST# when configured as shown in Figure 61 meets this 
requirement.  RSMRST# should have a weak external pull-down to ground and INTRUDER# should 
have a weak external pull-up to VCCRTC. This will prevent these nodes from floating in G3, and 
correspondingly will prevent ICCRTC leakage that can cause excessive coin-cell drain. The PWROK 
input signal should also be configured with an external weak pull-down. 

The effective impedance of the speaker and codec circuitry on the SPKR signal line must be greater than 
50 k

Ω

. Otherwise, the TCO Timer Reboot function will be disabled erroneously. SPKR is used both as 

the output signal to the system speaker and as a functional strap. The strap function enables or disables 
the “TCO Timer Reboot function,” depending on the state of the SPKR pin on the rising edge of 
POWEROK. When enabled, the ICH2 sends an SMI# to the processor when a TCO timer timeout 
occurs. The status of this strap is readable via the NO_REBOOT bit (bit 1, D31: F0, offset D4h). The 
SPKR signal has a weak integrated pull-up resistor, which is enabled only during boot/reset. Therefore, 
its default state when the pin is a “no connect” is a logical one or enabled. To disable this feature, a 
jumper can be populated to pull the signal line low (see Figure 62). The value of the pull-down must be 
such that the voltage divider caused by the pull-down and integrated pull-up resistors will be read as a