Intel 820E Benutzerhandbuch
Intel
®
820E Chipset
R
190
Design
Guide
Figure 104. Example 3.3V/5V REF Sequencing Circuitry
VCC Supply
(3.3 V)
5 V Supply
1 K
1 µF
To System
VREF
To System
6.1.5. Excessive Power Consumption by 64/72-Mbit RDRAM
Some 64/72-Mbit RDRAM devices interpret non-broadcast, device-directed commands as broadcast
commands. These commands are the SET_FAST_CLOCK, SET_RESET, and CLEAR_RESET
commands. RDRAM devices consume more current during these initialization steps than during normal
operation. If these devices accept device-directed commands as broadcast commands, the device cannot
be reset/initialized serially. All devices must be reset/initialize simultaneously. This will result in
excessive current draw during the initialization of memory. The amount of excessive current will depend
on the number of devices and the frequency used. The worst-case current draw is 7.5 A, in a system with
32 devices and a frequency of 400 MHz. There are two potential solutions:
commands. These commands are the SET_FAST_CLOCK, SET_RESET, and CLEAR_RESET
commands. RDRAM devices consume more current during these initialization steps than during normal
operation. If these devices accept device-directed commands as broadcast commands, the device cannot
be reset/initialized serially. All devices must be reset/initialize simultaneously. This will result in
excessive current draw during the initialization of memory. The amount of excessive current will depend
on the number of devices and the frequency used. The worst-case current draw is 7.5 A, in a system with
32 devices and a frequency of 400 MHz. There are two potential solutions:
1. Reduce the clock frequency during initialization (Section 6.1.5.1).
2. Increase the current capability of the 2.5 V voltage regulator (Section 6.1.5.2).
2. Increase the current capability of the 2.5 V voltage regulator (Section 6.1.5.2).
6.1.5.1.
Option 1: Reduce the Clock Frequency During Initialization
Tie a single core well GPO with a default high state to both the S0 and S1 pins of the DRCG (i.e., tie S0
and S1 together and then connect to a GPO as shown in Figure 105). When the core power supply to the
system is turned on, the DRCG enters a test mode and the output frequency will match the input
REFCLK frequency. For details regarding this DRCG mode, refer to the latest DRCG specification.
When the DRCG output clock is slowed down, the power consumed by the 2.5 V power supply is
reduced. After the SetR/ClrR commands have been issued, the BIOS drives the GPO low to bring the
DRCG back to normal operation.
and S1 together and then connect to a GPO as shown in Figure 105). When the core power supply to the
system is turned on, the DRCG enters a test mode and the output frequency will match the input
REFCLK frequency. For details regarding this DRCG mode, refer to the latest DRCG specification.
When the DRCG output clock is slowed down, the power consumed by the 2.5 V power supply is
reduced. After the SetR/ClrR commands have been issued, the BIOS drives the GPO low to bring the
DRCG back to normal operation.
Note: If a default-low GPO is used, during power-up all devices may come up in the standby state at full speed;
this requires more power.