Intel 820E Benutzerhandbuch

Design Guide 

 

27 

This chapter documents the motherboard layout and routing guidelines for Intel 820E chipset-based 
systems. This chapter does not discuss the functional aspects of any bus or the layout guidelines for an 
add-in device. 

Caution:  If the guidelines in this document are not followed, it is very important to complete thorough signal 

integrity and timing simulations for each design. Even if the guidelines are followed, critical signals still 
should be simulated to ensure proper signal integrity and flight time. As bus speeds increase, it is 
imperative that the guidelines documented be followed precisely. Any deviation from these guidelines 
must be simulated! 

The trace impedance typically noted (i.e., 60 

Ω

 ± 10%) is the “nominal” trace impedance. That is, it is 

the impedance of a trace when not subjected to the fields created by changing the current in neighboring 
traces. When calculating flight times, it is important to consider the minimum and maximum impedance 
of a trace based on the switching of neighboring traces. This trace-to-trace coupling can be minimized by 
using wider spaces between the traces. In addition, these wider spaces reduce crosstalk and settling time. 

Coupling between two traces is a function of the coupled length, the distance separating the traces, the 
signal edge rate, and the degree of mutual capacitance and inductance. To minimize the effects of trace-
to-trace coupling, the routing guidelines documented in this chapter should be followed. In addition, the 
PCB should be fabricated as documented in Section 5.1. 

Except where noted, all recommendations in this chapter assume 5 mil-wide traces. If the trace width is 
greater than 5 mils, then the trace spacing requirements must be adjusted accordingly (and linearly). For 
example, this chapter recommends routing most AGP signals with 5 mil traces on 20 mil spaces (1:4). If 
6 mil traces are used, then 24 mil spaces must be used (also 1:4). Using a wider trace—and therefore 
wider spaces—will make routing more difficult. 

Additionally, these routing guidelines are created using the stack-up described in Section 5.1. If this 
stack-up is not used, extremely thorough simulations of every interface must be completed. Using a 
thicker dielectric (prepreg) will make routing very difficult or impossible. 

The quadrant layouts shown are approximate and the exact ball assignments should be used to conduct 
routing analysis. These quadrant layouts are designed for use during component placement.