Intel 820E Benutzerhandbuch

Design Guide 

 

65 

The maximum total AGP clock skew (between the MCH and the graphics component) is 1 ns for all data 
transfer modes. This 1 ns includes skew and jitter that originates on the motherboard, add-in card, and 
clock synthesizer. Clock skew must be evaluated not only at a single threshold voltage, but at all points 
on the clock edge that fall within the switching range. The 1-ns skew budget is divided such that the 
motherboard is allotted 0.9 ns of clock skew. (The motherboard designer determines how the 0.9 ns are 
allocated between the board and the synthesizer.) For the Intel 820E chipset platform’s AGP clock 
routing guidelines, refer to Chapter 4 Clocking. 

The following routing guidelines are recommended for the optimal system design. The main focus of 
these guidelines is the minimization of signal integrity problems on the AGP interface of the Intel 820E 
chipset’s MCH. The following guidelines are not intended to replace thorough system validation on Intel 
820E chipset-based products. 

• 

For V

DDQ

 decoupling, at least six 0.01-

µ

F capacitors are required, of which at least four must be 

within 70 mils of the outer row of balls on the MCH. (See Figure 37.) 

• 

Evenly distribute the placement of decoupling capacitors in the AGP interface signal field. 

• 

Use a low-ESL ceramic capacitor (e.g., 0603 body type, X7R dielectric). 

• 

In addition to the minimum decoupling capacitors, bypass capacitors should be placed at vias that 
transition AGP signals from one reference signal plane to another. In a typical four-layer PCB 
design, the signals transition from one side of the board to the other. 

• 

One extra 0.01-

µ

F capacitor is required per 10 vias. The capacitor should be placed as close as 

possible to the center of the via field. 

• 

Ensure that the AGP connector is well decoupled, as described in the AGP Design Guide, Revision 
1.0 (Section 1.5.3.3). 

Note:  To add the decoupling capacitors as close as possible to the MCH and/or close to the vias, the trace 

spacing may be reduced as the traces go around each capacitor. The narrowing of the space between 
traces should be minimal and for as short a distance as possible (1 inch max.).