Intel 820E Benutzerhandbuch

Design Guide 

 

79 

• 

Distribute V

TT

 with a wide trace. A 0.050 inch minimum trace is recommended to minimize DC 

losses. Route the V

TT

 trace to all components on the host bus. Be sure to include decoupling 

capacitors. Guidelines for V

TT

 distribution and decoupling are contained in the Intel

 III Processor for the PGA370 Socket. 

• 

PV

REF

 should be generated with one voltage divider between the MCH and the processor for all 

V

REF

 pins. Be sure to include decoupling capacitors. Guidelines for V

REF

 distribution and 

decoupling are contained in the Intel

III Processor for the PGA370 Socket. Regarding special-case AGTL+ signals for simulation, there 
are six AGTL+ signals that can be driven simultaneously by more than one agent. These signals may 
require extra attention during the layout and validation portions of the design. When a signal is 
asserted (driven low) by two agents on the same clock edge, the two falling wavefronts will meet at 
some point on the bus. This can create a large undershoot, followed by ringback, which may violate 
the ringback specifications. This “wired-OR” situation should be simulated for the following 
signals: AERR#, BERR#, BINIT#, BNR#, HIT#, and HITM#. 

This section contains guidelines for connecting and routing the ICH2 IDE interface. The ICH2 has two 
independent IDE channels. This section provides guidelines for IDE connector cabling and motherboard 
design, including component and resistor placement, and signal termination for both IDE channels. The 
ICH2 has integrated the series resistors typically required on the IDE data signals (PDD[15:0] and 
SDD[15:0]) running to the two ATA connectors. Intel does not anticipate requiring additional series 
termination, but OEMs should verify motherboard signal integrity through simulation. Additional 
external 0 

Ω

 resistors can be incorporated into the design to address possible noise issues on the 

motherboard. The additional resistor layout increases flexibility by offering stuffing options at a later 
date. 

The IDE interface can be routed with 5 mil traces on 7 mil spaces, and must be less than 8 inches long 
(from ICH2 to IDE connector). Additionally, the shortest IDE signal (on a given IDE channel) must be 
less than 0.5 inch shorter than the longest IDE signal (on that channel). 

• 

Length of cable: Each IDE cable must be 

≤

18 inches. 

• 

Capacitance: Less than 30 pF. 

• 

Placement: A maximum of 6 inches between drive connectors on the cable. If a single drive is 
placed on the cable, it should be placed at the end of the cable. If a second drive is placed on the 
same cable, it should be placed on the connector next closest to the end of the cable (6 inches away 
from the end of the cable).  

• 

Grounding: Provide a direct low-impedance chassis path between the motherboard ground and the 
hard disk drives. 

• 

ICH2 placement: The ICH2 must be placed 

≤

8 inches from the ATA connector(s).