Intel 820E Benutzerhandbuch

Intel

820E Chipset

Design

Guide

Figures

Figure 1. Intel

820E Chipset Platform Performance Desktop Block Diagram ........................18

Figure 2. Intel

820E Chipset Platform Performance Desktop Block Diagram

(with ISA Bridge)........................................................................................................18

Figure 3. Intel

820E Chipset Platform Dual-Processor Performance Desktop Block

Diagram.....................................................................................................................19

Figure 4. (A-C) AC’97 Connections ..........................................................................................24

Figure 5. MCH 324-Ball µBGA* CSP Quadrant Layout (Top View) .........................................28

Figure 6. ICH2 360-Ball EBGA Quadrant Layout (Top View) ...................................................28

Figure 7. Sample ATX and NLX MCH/ICH2 Component Placement.......................................29

Figure 8. Primary-Side MCH Core Routing Example (ATX).....................................................30

Figure 9. Secondary-Side MCH Core Routing Example (ATX) ................................................31

Figure 10. Data Strobing Example ...........................................................................................32

Figure 11. Effect of Crosstalk on Strobe Signal .......................................................................32

Figure 12. RIMM Diagram ........................................................................................................33

Figure 13. RSL Routing Dimensions ........................................................................................35

Figure 14. RSL Routing Diagram .............................................................................................36

Figure 15. Primary-Side RSL Breakout Example .....................................................................36

Figure 16. Secondary-Side RSL Breakout Example ................................................................37

Figure 17. Direct RDRAM Termination.....................................................................................38

Figure 18. Direct RDRAM* Termination Example ....................................................................39

Figure 19. Incorrect Direct RDRAM* Ground Plane Referencing.............................................40

Figure 20. Direct RDRAM* Ground Plane Reference...............................................................40

Figure 21. Connector Compensation Example ........................................................................43

Figure 22. Section A (See Note), Top Layer.............................................................................44

Figure 23. Section A (See Note), Bottom Layer .......................................................................45

Figure 24. Section B (See Note), Top Layer.............................................................................46

Figure 25. Section B (See Note), Bottom Layer .......................................................................47

Figure 26. Top-Layer CTAB with RSL Signal Routed on the Same Layer (C

EFF

= 0.8 pF) ......48

Figure 27. Bottom-Layer CTAB with RSL Signal Routed on the Same Layer

EFF

= 1.35 pF).......................................................................................................48

Figure 28. Bottom-Layer CTABs Split across the Top and Bottom Layer to Achieve an

Effect C

EFF

~1.35 pF...............................................................................................49

Figure 29. RSL Signal Layer Alternation ..................................................................................50

Figure 30. Example of RDRAM Trace Length Matching ..........................................................51

Figure 31. “Dummy” Via vs. “Real” Via.....................................................................................52

Figure 32. RAMREF Generation Example Circuit ....................................................................54

Figure 33. High-Speed CMOS Termination..............................................................................55

Figure 34. SIO Routing Example..............................................................................................55

Figure 35. RDRAM CMOS Shunt Transistor ............................................................................56

Figure 36. AGP 2×/4× Routing Example for Interfaces < 6 Inches ..........................................63

Figure 37. Top Signal Layer .....................................................................................................66

Figure 38. AGP V

DDQ

Generation Example Circuit ...................................................................68

Figure 39. AGP 2.0 V

REF

Generation and Distribution ..............................................................69

Figure 40. AGP Left-Handed Retention Mechanism ................................................................72

Figure 41. AGP Left-Handed RM Keep-Out Information..........................................................73

Figure 42. Hub Interface Signal Routing Example ...................................................................74

Figure 43. 8-Bit Hub Interface with a Shared Reference Divider Circuit

(Normal/Single Mode) .............................................................................................76

Figure 44. 8-Bit Hub Interface with Locally Generated Reference Divider Circuits

(Normal/Local Mode)...............................................................................................76

Figure 45. Ground Plane Reference (4-Layer Motherboard)....................................................78

Figure 46. Combination Host-Side/Device-Side IDE Cable Detection .....................................81