Motorola CPCI-6115 Benutzerhandbuch
6
CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)
115
Remote Start via the PCI Bus
6.1
Overview
This chapter describes the remote interface provided by the firmware to the host CPU via the
CompactPCI bus. This interface facilitates the host obtaining information about the board,
downloading code and/or data, and execution of the downloaded program.
CompactPCI bus. This interface facilitates the host obtaining information about the board,
downloading code and/or data, and execution of the downloaded program.
For boards where the 21555 is disabled, the remote start function, as described in the
MOTLoad Firmware Package User’s Manual will not work.
MOTLoad Firmware Package User’s Manual will not work.
Applications may also be downloaded to the CPCI-6115 via one of the PCI bus windows
provided by the PCI-to-PCI bridge. This method is faster than using the MOTLoad remote
interface and may be preferable to use for large downloads.
provided by the PCI-to-PCI bridge. This method is faster than using the MOTLoad remote
interface and may be preferable to use for large downloads.
6.2
Register Description
MOTLoad uses one of the scratch pad registers of the Intel 2155x PCI-to-PCI bridge as the
interboard communication channel. This scratch pad register is logically divided into five
sections:
interboard communication channel. This scratch pad register is logically divided into five
sections:
z
An ownership flag. When set, indicates that the host ‘owns’ the register and is free to write
a new command into it. It also indicates that the previous command, if any, has been
completed and the results, if any, have been returned to the register. When the host writes
a new command to the register, it must clear the ownership flag to indicate the register
contains a command to be processed.
a new command into it. It also indicates that the previous command, if any, has been
completed and the results, if any, have been returned to the register. When the host writes
a new command to the register, it must clear the ownership flag to indicate the register
contains a command to be processed.
z
A ‘command opcode’. This field is a numeric field that specifies the command the host
wants performed.
wants performed.
z
An error flag, which is used to provide command completion status to the host CPU.
z
A ‘command options field. This field further qualifies the specifics of the command to be
performed. The meaning of the option field is specific to each command opcode.
performed. The meaning of the option field is specific to each command opcode.
z
A command data and result field. This field provides the data, if any, needed by the
command and provides the response from MOTLoad upon command completion. The
meaning of the bits in this field are specific to each command opcode.
command and provides the response from MOTLoad upon command completion. The
meaning of the bits in this field are specific to each command opcode.
Additionally, certain commands require more information than can be contained within the data
and result fields of the scratch pad register. To provide this information, the interface provides
four ‘virtual’ registers. The contents of these registers are used in certain commands. The
contents of the registers can be accessed via commands issued through the scratch register.
These registers are identified as VR0, VR1, VR2 and VR3.
and result fields of the scratch pad register. To provide this information, the interface provides
four ‘virtual’ registers. The contents of these registers are used in certain commands. The
contents of the registers can be accessed via commands issued through the scratch register.
These registers are identified as VR0, VR1, VR2 and VR3.
During reset startup, the command/response register is written with a specific reset pattern.
This indicates that the local CPU has been reset and is ready to accept commands through the
command/response register.
This indicates that the local CPU has been reset and is ready to accept commands through the
command/response register.