Intel 253668-032US Benutzerhandbuch
Vol. 3 4-37
PAGING
4.9
PAGING AND MEMORY TYPING
The memory type of a memory access refers to the type of caching used for that
access. Chapter 11, “Memory Cache Control” provides many details regarding
memory typing in the Intel-64 and IA-32 architectures. This section describes how
paging contributes to the determination of memory typing.
The way in which paging contributes to memory typing depends on whether the
processor supports the Page Attribute Table (PAT; see Section 11.12).
access. Chapter 11, “Memory Cache Control” provides many details regarding
memory typing in the Intel-64 and IA-32 architectures. This section describes how
paging contributes to the determination of memory typing.
The way in which paging contributes to memory typing depends on whether the
processor supports the Page Attribute Table (PAT; see Section 11.12).
1
4.9.1 and Section 4.9.2 explain how paging contributes to memory typing depending
on whether the PAT is supported.
on whether the PAT is supported.
4.9.1
Paging and Memory Typing When the PAT is Not Supported
(Pentium Pro and Pentium II Processors)
NOTE
The PAT is supported on all processors that support IA-32e paging.
Thus, this section applies only to 32-bit paging and PAE paging.
Thus, this section applies only to 32-bit paging and PAE paging.
If the PAT is not supported, paging contributes to memory typing in conjunction with
the memory-type range registers (MTRRs) as specified in Table 11-6 in Section
11.5.2.1.
For any access to a physical address, the table combines the memory type specified
for that physical address by the MTRRs with a PCD value and a PWT value. The latter
two values are determined as follows:
the memory-type range registers (MTRRs) as specified in Table 11-6 in Section
11.5.2.1.
For any access to a physical address, the table combines the memory type specified
for that physical address by the MTRRs with a PCD value and a PWT value. The latter
two values are determined as follows:
•
For an access to a PDE with 32-bit paging, the PCD and PWT values come from
CR3.
CR3.
•
For an access to a PDE with PAE paging, the PCD and PWT values come from the
relevant PDPTE register.
relevant PDPTE register.
•
For an access to a PTE, the PCD and PWT values come from the relevant PDE.
•
For an access to the physical address that is the translation of a linear address,
the PCD and PWT values come from the relevant PTE (if the translation uses a 4-
KByte page) or the relevant PDE (otherwise).
the PCD and PWT values come from the relevant PTE (if the translation uses a 4-
KByte page) or the relevant PDE (otherwise).
4.9.2
Paging and Memory Typing When the PAT is Supported
(Pentium III and More Recent Processor Families)
If the PAT is supported, paging contributes to memory typing in conjunction with the
PAT and the memory-type range registers (MTRRs) as specified in Table 11-7 in
Section 11.5.2.2.
PAT and the memory-type range registers (MTRRs) as specified in Table 11-7 in
Section 11.5.2.2.
1. The PAT is supported on Pentium III and more recent processor families. See Section 4.1.4 for
how to determine whether the PAT is supported.