Intel 253668-032US Benutzerhandbuch
4-44 Vol. 3
PAGING
For example, if the R/W flag is 0 in a PML4E, then the R/W flag will be 0 in any PDPTE-
cache entry for a PDPTE from the page-directory-pointer table referenced by that
PML4E. This is because the R/W flag of each such PDPTE-cache entry is the logical-
AND of the R/W flags in the appropriate PML4E and PDPTE.
The paging-structure caches contain information only from paging-structure entries
that reference other paging structures (and not those that map pages). Because the
G flag is not used in such paging-structure entries, the global-page feature does not
affect the behavior of the paging-structure caches.
The processor may create entries in paging-structure caches for translations
required for prefetches and for accesses that are a result of speculative execution
that would never actually occur in the executed code path.
A processor may or may not implement any of the paging-structure caches. Software
should rely on neither their presence nor their absence. The processor may invalidate
entries in these caches at any time. Because the processor may create the cache
entries at the time of translation and not update them following subsequent modifi-
cations to the paging structures in memory, software should take care to invalidate
the cache entries appropriately when causing such modifications. The invalidation of
TLBs and the paging-structure caches is described in Section 4.10.3.
cache entry for a PDPTE from the page-directory-pointer table referenced by that
PML4E. This is because the R/W flag of each such PDPTE-cache entry is the logical-
AND of the R/W flags in the appropriate PML4E and PDPTE.
The paging-structure caches contain information only from paging-structure entries
that reference other paging structures (and not those that map pages). Because the
G flag is not used in such paging-structure entries, the global-page feature does not
affect the behavior of the paging-structure caches.
The processor may create entries in paging-structure caches for translations
required for prefetches and for accesses that are a result of speculative execution
that would never actually occur in the executed code path.
A processor may or may not implement any of the paging-structure caches. Software
should rely on neither their presence nor their absence. The processor may invalidate
entries in these caches at any time. Because the processor may create the cache
entries at the time of translation and not update them following subsequent modifi-
cations to the paging structures in memory, software should take care to invalidate
the cache entries appropriately when causing such modifications. The invalidation of
TLBs and the paging-structure caches is described in Section 4.10.3.
4.10.2.2 Using the Paging-Structure Caches to Translate Linear Addresses
When a linear address is accessed, the processor uses a procedure such as the
following to determine the physical address to which it translates and whether the
access should be allowed:
following to determine the physical address to which it translates and whether the
access should be allowed:
•
If the processor finds a TLB entry for the page number of the linear address, it
may use the physical address, access rights, and other attributes from that entry.
may use the physical address, access rights, and other attributes from that entry.
•
If the processor does not find a TLB entry, it may use the upper bits of the linear
address to select an entry from the PDE cache (Section 4.10.2.1 indicates which
bits are used in each paging mode). It can then use that entry to complete the
translation process (locating a PTE, etc.) as if it had traversed the PDE (and, for
IA-32e paging, the PDPTE and PML4) corresponding to the PDE-cache entry.
address to select an entry from the PDE cache (Section 4.10.2.1 indicates which
bits are used in each paging mode). It can then use that entry to complete the
translation process (locating a PTE, etc.) as if it had traversed the PDE (and, for
IA-32e paging, the PDPTE and PML4) corresponding to the PDE-cache entry.
•
The following items apply when IA-32e paging is used:
— If the processor does not find a TLB entry or a PDE-cache entry, it may use
— If the processor does not find a TLB entry or a PDE-cache entry, it may use
bits 47:30 of the linear address to select an entry from the PDPTE cache. It
can then use that entry to complete the translation process (locating a PDE,
etc.) as if it had traversed the PDPTE and the PML4 corresponding to the
PDPTE-cache entry.
can then use that entry to complete the translation process (locating a PDE,
etc.) as if it had traversed the PDPTE and the PML4 corresponding to the
PDPTE-cache entry.
— If the processor does not find a TLB entry, a PDE-cache entry, or a PDPTE-
cache entry, it may use bits 47:39 of the linear address to select an entry
from the PML4 cache. It can then use that entry to complete the translation
process (locating a PDPTE, etc.) as if it had traversed the corresponding
PML4.
from the PML4 cache. It can then use that entry to complete the translation
process (locating a PDPTE, etc.) as if it had traversed the corresponding
PML4.