Intel 253668-032US Benutzerhandbuch
Vol. 3 7-15
TASK MANAGEMENT
rules control access to a TSS, software does not need to perform explicit privilege
checks on a task switch.
Table 7-1 shows the exception conditions that the processor checks for when
switching tasks. It also shows the exception that is generated for each check if an
error is detected and the segment that the error code references. (The order of the
checks in the table is the order used in the P6 family processors. The exact order is
model specific and may be different for other IA-32 processors.) Exception handlers
designed to handle these exceptions may be subject to recursive calls if they attempt
to reload the segment selector that generated the exception. The cause of the excep-
tion (or the first of multiple causes) should be fixed before reloading the selector.
checks on a task switch.
Table 7-1 shows the exception conditions that the processor checks for when
switching tasks. It also shows the exception that is generated for each check if an
error is detected and the segment that the error code references. (The order of the
checks in the table is the order used in the P6 family processors. The exact order is
model specific and may be different for other IA-32 processors.) Exception handlers
designed to handle these exceptions may be subject to recursive calls if they attempt
to reload the segment selector that generated the exception. The cause of the excep-
tion (or the first of multiple causes) should be fixed before reloading the selector.
Table 7-1. Exception Conditions Checked During a Task Switch
Condition Checked
Exception
1
Error Code
Reference
2
Segment selector for a TSS descriptor references
the GDT and is within the limits of the table.
#GP
#TS (for IRET)
#TS (for IRET)
New Task’s TSS
TSS descriptor is present in memory.
#NP
New Task’s TSS
TSS descriptor is not busy (for task switch initiated
by a call, interrupt, or exception).
#GP (for JMP, CALL,
INT)
Task’s back-link TSS
TSS descriptor is not busy (for task switch initiated
by an IRET instruction).
#TS (for IRET)
New Task’s TSS
TSS segment limit greater than or equal to 108 (for
32-bit TSS) or 44 (for 16-bit TSS).
#TS
New Task’s TSS
Registers are loaded from the values in the TSS.
LDT segment selector of new task is valid
LDT segment selector of new task is valid
3
.
#TS
New Task’s LDT
Code segment DPL matches segment selector RPL.
#TS
New Code Segment
SS segment selector is valid
2
.
#TS
New Stack Segment
Stack segment is present in memory.
#SS
New Stack Segment
Stack segment DPL matches CPL.
#TS
New stack segment
LDT of new task is present in memory.
#TS
New Task’s LDT
CS segment selector is valid
3
.
#TS
New Code Segment
Code segment is present in memory.
#NP
New Code Segment
Stack segment DPL matches selector RPL.
#TS
New Stack Segment
DS, ES, FS, and GS segment selectors are valid
3
.
#TS
New Data Segment
DS, ES, FS, and GS segments are readable.
#TS
New Data Segment