Intel 253668-032US Benutzerhandbuch
Vol. 3 8-3
MULTIPLE-PROCESSOR MANAGEMENT
software to manage the fairness of semaphores and exclusive locking
functions.
functions.
The mechanisms for handling locked atomic operations have evolved with the
complexity of IA-32 processors. More recent IA-32 processors (such as the
Pentium 4, Intel Xeon, and P6 family processors) and Intel 64 provide a more refined
locking mechanism than earlier processors. These mechanisms are described in the
following sections.
complexity of IA-32 processors. More recent IA-32 processors (such as the
Pentium 4, Intel Xeon, and P6 family processors) and Intel 64 provide a more refined
locking mechanism than earlier processors. These mechanisms are described in the
following sections.
8.1.1
Guaranteed Atomic Operations
The Intel486 processor (and newer processors since) guarantees that the following
basic memory operations will always be carried out atomically:
basic memory operations will always be carried out atomically:
•
Reading or writing a byte
•
Reading or writing a word aligned on a 16-bit boundary
•
Reading or writing a doubleword aligned on a 32-bit boundary
The Pentium processor (and newer processors since) guarantees that the following
additional memory operations will always be carried out atomically:
additional memory operations will always be carried out atomically:
•
Reading or writing a quadword aligned on a 64-bit boundary
•
16-bit accesses to uncached memory locations that fit within a 32-bit data bus
The P6 family processors (and newer processors since) guarantee that the following
additional memory operation will always be carried out atomically:
additional memory operation will always be carried out atomically:
•
Unaligned 16-, 32-, and 64-bit accesses to cached memory that fit within a cache
line
line
Accesses to cacheable memory that are split across bus widths, cache lines, and
page boundaries are not guaranteed to be atomic by the Intel Core 2 Duo, Intel
Atom, Intel Core Duo, Pentium M, Pentium 4, Intel Xeon, P6 family, Pentium, and
Intel486 processors. The Intel Core 2 Duo, Intel Atom, Intel Core Duo, Pentium M,
Pentium 4, Intel Xeon, and P6 family processors provide bus control signals that
permit external memory subsystems to make split accesses atomic; however,
nonaligned data accesses will seriously impact the performance of the processor and
should be avoided.
page boundaries are not guaranteed to be atomic by the Intel Core 2 Duo, Intel
Atom, Intel Core Duo, Pentium M, Pentium 4, Intel Xeon, P6 family, Pentium, and
Intel486 processors. The Intel Core 2 Duo, Intel Atom, Intel Core Duo, Pentium M,
Pentium 4, Intel Xeon, and P6 family processors provide bus control signals that
permit external memory subsystems to make split accesses atomic; however,
nonaligned data accesses will seriously impact the performance of the processor and
should be avoided.
8.1.2 Bus
Locking
Intel 64 and IA-32 processors provide a LOCK# signal that is asserted automatically
during certain critical memory operations to lock the system bus or equivalent link.
While this output signal is asserted, requests from other processors or bus agents for
control of the bus are blocked. Software can specify other occasions when the LOCK
semantics are to be followed by prepending the LOCK prefix to an instruction.
In the case of the Intel386, Intel486, and Pentium processors, explicitly locked
instructions will result in the assertion of the LOCK# signal. It is the responsibility of
during certain critical memory operations to lock the system bus or equivalent link.
While this output signal is asserted, requests from other processors or bus agents for
control of the bus are blocked. Software can specify other occasions when the LOCK
semantics are to be followed by prepending the LOCK prefix to an instruction.
In the case of the Intel386, Intel486, and Pentium processors, explicitly locked
instructions will result in the assertion of the LOCK# signal. It is the responsibility of