Intel 253668-032US Benutzerhandbuch
8-6 Vol. 3
MULTIPLE-PROCESSOR MANAGEMENT
ence weakly ordered memory types (such as the WC memory type) may not be seri-
alized.
Locked instructions should not be used to insure that data written can be fetched as
instructions.
alized.
Locked instructions should not be used to insure that data written can be fetched as
instructions.
NOTE
The locked instructions for the current versions of the Pentium 4,
Intel Xeon, P6 family, Pentium, and Intel486 processors allow data
written to be fetched as instructions. However, Intel recommends
that developers who require the use of self-modifying code use a
different synchronizing mechanism, described in the following
sections.
Intel Xeon, P6 family, Pentium, and Intel486 processors allow data
written to be fetched as instructions. However, Intel recommends
that developers who require the use of self-modifying code use a
different synchronizing mechanism, described in the following
sections.
8.1.3
Handling Self- and Cross-Modifying Code
The act of a processor writing data into a currently executing code segment with
the intent of executing that data as code is called self-modifying code. IA-32
processors exhibit model-specific behavior when executing self-modified code,
depending upon how far ahead of the current execution pointer the code has been
modified.
As processor microarchitectures become more complex and start to speculatively
execute code ahead of the retirement point (as in P6 and more recent processor
families), the rules regarding which code should execute, pre- or post-modification,
become blurred. To write self-modifying code and ensure that it is compliant with
current and future versions of the IA-32 architectures, use one of the following
coding options:
the intent of executing that data as code is called self-modifying code. IA-32
processors exhibit model-specific behavior when executing self-modified code,
depending upon how far ahead of the current execution pointer the code has been
modified.
As processor microarchitectures become more complex and start to speculatively
execute code ahead of the retirement point (as in P6 and more recent processor
families), the rules regarding which code should execute, pre- or post-modification,
become blurred. To write self-modifying code and ensure that it is compliant with
current and future versions of the IA-32 architectures, use one of the following
coding options:
(* OPTION 1 *)
Store modified code (as data) into code segment;
Jump to new code or an intermediate location;
Execute new code;
Store modified code (as data) into code segment;
Jump to new code or an intermediate location;
Execute new code;
(* OPTION 2 *)
Store modified code (as data) into code segment;
Execute a serializing instruction; (* For example, CPUID instruction *)
Execute new code;
Store modified code (as data) into code segment;
Execute a serializing instruction; (* For example, CPUID instruction *)
Execute new code;
The use of one of these options is not required for programs intended to run on the
Pentium or Intel486 processors, but are recommended to insure compatibility with
the P6 and more recent processor families.
Self-modifying code will execute at a lower level of performance than non-self-modi-
fying or normal code. The degree of the performance deterioration will depend upon
the frequency of modification and specific characteristics of the code.
Pentium or Intel486 processors, but are recommended to insure compatibility with
the P6 and more recent processor families.
Self-modifying code will execute at a lower level of performance than non-self-modi-
fying or normal code. The degree of the performance deterioration will depend upon
the frequency of modification and specific characteristics of the code.