Intel 253668-032US Benutzerhandbuch
Vol. 3 8-47
MULTIPLE-PROCESSOR MANAGEMENT
8.8.3
Performance Monitoring Counters
Performance counters and their companion control MSRs are shared between two
logical processors sharing a processor core if the processor core supports Intel
Hyper-Threading Technology and is based on Intel NetBurst microarchitecture. They
are not shared between logical processors in different cores or different physical
packages. As a result, software must manage the use of these resources, based on
the topology of performance monitoring resources. Performance counter interrupts,
events, and precise event monitoring support can be set up and allocated on a per
thread (per logical processor) basis.
See Section 30.9, “Performance Monitoring and Intel Hyper-Threading Technology in
Processors Based on Intel NetBurst Microarchitecture.”
logical processors sharing a processor core if the processor core supports Intel
Hyper-Threading Technology and is based on Intel NetBurst microarchitecture. They
are not shared between logical processors in different cores or different physical
packages. As a result, software must manage the use of these resources, based on
the topology of performance monitoring resources. Performance counter interrupts,
events, and precise event monitoring support can be set up and allocated on a per
thread (per logical processor) basis.
See Section 30.9, “Performance Monitoring and Intel Hyper-Threading Technology in
Processors Based on Intel NetBurst Microarchitecture.”
8.8.4 IA32_MISC_ENABLE
MSR
Some bit fields in IA32_MISC_ENABLE MSR (MSR address 1A0H) may be shared
between two logical processors sharing a processor core, or may be shared between
different cores in a physical processor. See Appendix B, “Model-Specific Registers
(MSRs)”.
between two logical processors sharing a processor core, or may be shared between
different cores in a physical processor. See Appendix B, “Model-Specific Registers
(MSRs)”.
8.8.5
MICROCODE UPDATE Resources
Microcode update facilities are shared between two logical processors sharing a
processor core if the physical package supports Intel Hyper-Threading Technology.
They are not shared between logical processors in different cores or different phys-
ical packages. Either logical processor that has access to the microcode update
facility can initiate an update.
Each logical processor has its own BIOS signature MSR (IA32_BIOS_SIGN_ID at MSR
address 8BH). When a logical processor performs an update for the physical
processor, the IA32_BIOS_SIGN_ID MSRs for resident logical processors are
updated with identical information. If logical processors initiate an update simulta-
neously, the processor core provides the synchronization needed to ensure that only
one update is performed at a time.
processor core if the physical package supports Intel Hyper-Threading Technology.
They are not shared between logical processors in different cores or different phys-
ical packages. Either logical processor that has access to the microcode update
facility can initiate an update.
Each logical processor has its own BIOS signature MSR (IA32_BIOS_SIGN_ID at MSR
address 8BH). When a logical processor performs an update for the physical
processor, the IA32_BIOS_SIGN_ID MSRs for resident logical processors are
updated with identical information. If logical processors initiate an update simulta-
neously, the processor core provides the synchronization needed to ensure that only
one update is performed at a time.
8.9
PROGRAMMING CONSIDERATIONS FOR HARDWARE
MULTI-THREADING CAPABLE PROCESSORS
In a multi-threading environment, there may be certain hardware resources that are
physically shared at some level of the hardware topology. In the multi-processor
systems, typically bus and memory sub-systems are physically shared between
multiple sockets. Within a hardware multi-threading capable processors, certain
resources are provided for each processor core, while other resources may be
physically shared at some level of the hardware topology. In the multi-processor
systems, typically bus and memory sub-systems are physically shared between
multiple sockets. Within a hardware multi-threading capable processors, certain
resources are provided for each processor core, while other resources may be