Intel 253668-032US Benutzerhandbuch
Vol. 3 8-51
MULTIPLE-PROCESSOR MANAGEMENT
For m = 0, m < N, m ++;
{ cumulative_width[m] = CPUID.(EAX=0BH, ECX= m): EAX[4:0]; }
BitWidth[0] = cumulative_width[0];
For m = 1, m < N, m ++;
{ cumulative_width[m] = CPUID.(EAX=0BH, ECX= m): EAX[4:0]; }
BitWidth[0] = cumulative_width[0];
For m = 1, m < N, m ++;
BitWidth[m] = cumulative_width[m] - cumulative_width[m-1];
Currently, only the following encoding of hierarchical level type are defined: 0
(invalid), 1 (SMT), and 2 (core). Software must not assume any “level type“ encoding
value to be related to any sub-leaf index, except sub-leaf 0.
Example 8-16 and Example 8-17 represent the general technique for using CPUID
leaf 0BH to enumerate processor topology of more than two levels of hierarchy inside
a physical package. Most processor families to date requires only “SMT” and “CORE”
levels within a physical package. The examples in later sections will focus on these
three-level topology only.
(invalid), 1 (SMT), and 2 (core). Software must not assume any “level type“ encoding
value to be related to any sub-leaf index, except sub-leaf 0.
Example 8-16 and Example 8-17 represent the general technique for using CPUID
leaf 0BH to enumerate processor topology of more than two levels of hierarchy inside
a physical package. Most processor families to date requires only “SMT” and “CORE”
levels within a physical package. The examples in later sections will focus on these
three-level topology only.
8.9.3
Hierarchical ID of Logical Processors in an MP System
For Intel 64 and IA-32 processors, system hardware establishes an 8-bit initial APIC
ID (or 32-bit APIC ID if the processor supports CPUID leaf 0BH) that is unique for
each logical processor following power-up or RESET (see Section 8.6.1). Each logical
processor on the system is allocated an initial APIC ID. BIOS may implement features
that tell the OS to support less than the total number of logical processors on the
system bus. Those logical processors that are not available to applications at runtime
are halted during the OS boot process. As a result, the number valid local APIC_IDs
that can be queried by affinitizing-current-thread-context (See Example 8-22) is
limited to the number of logical processors enabled at runtime by the OS boot
process.
Table 8-1 shows an example of the 8-bit APIC IDs that are initially reported for logical
processors in a system with four Intel Xeon MP processors that support Intel Hyper-
Threading Technology (a total of 8 logical processors, each physical package has two
processor cores and supports Intel Hyper-Threading Technology). Of the two logical
processors within a Intel Xeon processor MP, logical processor 0 is designated the
primary logical processor and logical processor 1 as the secondary logical processor.
ID (or 32-bit APIC ID if the processor supports CPUID leaf 0BH) that is unique for
each logical processor following power-up or RESET (see Section 8.6.1). Each logical
processor on the system is allocated an initial APIC ID. BIOS may implement features
that tell the OS to support less than the total number of logical processors on the
system bus. Those logical processors that are not available to applications at runtime
are halted during the OS boot process. As a result, the number valid local APIC_IDs
that can be queried by affinitizing-current-thread-context (See Example 8-22) is
limited to the number of logical processors enabled at runtime by the OS boot
process.
Table 8-1 shows an example of the 8-bit APIC IDs that are initially reported for logical
processors in a system with four Intel Xeon MP processors that support Intel Hyper-
Threading Technology (a total of 8 logical processors, each physical package has two
processor cores and supports Intel Hyper-Threading Technology). Of the two logical
processors within a Intel Xeon processor MP, logical processor 0 is designated the
primary logical processor and logical processor 1 as the secondary logical processor.