Intel 253668-032US Benutzerhandbuch
Vol. 3 8-73
MULTIPLE-PROCESSOR MANAGEMENT
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A high resolution timer within the processor (such as, the local APIC timer or the
time-stamp counter).
time-stamp counter).
For additional information, see the Intel® 64 and IA-32 Architectures Optimization
Reference Manual.
Reference Manual.
8.10.6.7 Place Locks and Semaphores in Aligned, 128-Byte Blocks of
Memory
When software uses locks or semaphores to synchronize processes, threads, or other
code sections; Intel recommends that only one lock or semaphore be present within
a cache line (or 128 byte sector, if 128-byte sector is supported). In processors based
on Intel NetBurst microarchitecture (which support 128-byte sector consisting of two
cache lines), following this recommendation means that each lock or semaphore
should be contained in a 128-byte block of memory that begins on a 128-byte
boundary. The practice minimizes the bus traffic required to service locks.
code sections; Intel recommends that only one lock or semaphore be present within
a cache line (or 128 byte sector, if 128-byte sector is supported). In processors based
on Intel NetBurst microarchitecture (which support 128-byte sector consisting of two
cache lines), following this recommendation means that each lock or semaphore
should be contained in a 128-byte block of memory that begins on a 128-byte
boundary. The practice minimizes the bus traffic required to service locks.