Intel 253668-032US Benutzerhandbuch
9-6 Vol. 3
PROCESSOR MANAGEMENT AND INITIALIZATION
9.1.4
First Instruction Executed
The first instruction that is fetched and executed following a hardware reset is
located at physical address FFFFFFF0H. This address is 16 bytes below the
processor’s uppermost physical address. The EPROM containing the software-
located at physical address FFFFFFF0H. This address is 16 bytes below the
processor’s uppermost physical address. The EPROM containing the software-
initialization code must be located at this address.
The address FFFFFFF0H is beyond the 1-MByte addressable range of the processor
while in real-address mode. The processor is initialized to this starting address as
follows. The CS register has two parts: the visible segment selector part and the
hidden base address part. In real-address mode, the base address is normally
formed by shifting the 16-bit segment selector value 4 bits to the left to produce a
20-bit base address. However, during a hardware reset, the segment selector in the
CS register is loaded with F000H and the base address is loaded with FFFF0000H. The
starting address is thus formed by adding the base address to the value in the EIP
register (that is, FFFF0000 + FFF0H = FFFFFFF0H).
The first time the CS register is loaded with a new value after a hardware reset, the
processor will follow the normal rule for address translation in real-address mode
(that is, [CS base address = CS segment selector * 16]). To insure that the base
address in the CS register remains unchanged until the EPROM based software-
initialization code is completed, the code must not contain a far jump or far call or
allow an interrupt to occur (which would cause the CS selector value to be changed).
The address FFFFFFF0H is beyond the 1-MByte addressable range of the processor
while in real-address mode. The processor is initialized to this starting address as
follows. The CS register has two parts: the visible segment selector part and the
hidden base address part. In real-address mode, the base address is normally
formed by shifting the 16-bit segment selector value 4 bits to the left to produce a
20-bit base address. However, during a hardware reset, the segment selector in the
CS register is loaded with F000H and the base address is loaded with FFFF0000H. The
starting address is thus formed by adding the base address to the value in the EIP
register (that is, FFFF0000 + FFF0H = FFFFFFF0H).
The first time the CS register is loaded with a new value after a hardware reset, the
processor will follow the normal rule for address translation in real-address mode
(that is, [CS base address = CS segment selector * 16]). To insure that the base
address in the CS register remains unchanged until the EPROM based software-
initialization code is completed, the code must not contain a far jump or far call or
allow an interrupt to occur (which would cause the CS selector value to be changed).
9.2
X87 FPU INITIALIZATION
Software-initialization code can determine the whether the processor contains an
x87 FPU by using the CPUID instruction. The code must then initialize the x87 FPU
and set flags in control register CR0 to reflect the state of the x87 FPU environment.
A hardware reset places the x87 FPU in the state shown in Table 9-1. This state is
different from the state the x87 FPU is placed in following the execution of an FINIT
or FNINIT instruction (also shown in Table 9-1). If the x87 FPU is to be used, the soft-
ware-initialization code should execute an FINIT/FNINIT instruction following a hard-
ware reset. These instructions, tag all data registers as empty, clear all the exception
masks, set the TOP-of-stack value to 0, and select the default rounding and precision
controls setting (round to nearest and 64-bit precision).
If the processor is reset by asserting the INIT# pin, the x87 FPU state is not changed.
x87 FPU by using the CPUID instruction. The code must then initialize the x87 FPU
and set flags in control register CR0 to reflect the state of the x87 FPU environment.
A hardware reset places the x87 FPU in the state shown in Table 9-1. This state is
different from the state the x87 FPU is placed in following the execution of an FINIT
or FNINIT instruction (also shown in Table 9-1). If the x87 FPU is to be used, the soft-
ware-initialization code should execute an FINIT/FNINIT instruction following a hard-
ware reset. These instructions, tag all data registers as empty, clear all the exception
masks, set the TOP-of-stack value to 0, and select the default rounding and precision
controls setting (round to nearest and 64-bit precision).
If the processor is reset by asserting the INIT# pin, the x87 FPU state is not changed.
9.2.1
Configuring the x87 FPU Environment
Initialization code must load the appropriate values into the MP, EM, and NE flags of
control register CR0. These bits are cleared on hardware reset of the processor.
Figure 9-2 shows the suggested settings for these flags, depending on the IA-32
processor being initialized. Initialization code can test for the type of processor
present before setting or clearing these flags.
control register CR0. These bits are cleared on hardware reset of the processor.
Figure 9-2 shows the suggested settings for these flags, depending on the IA-32
processor being initialized. Initialization code can test for the type of processor
present before setting or clearing these flags.