Intel 253668-032US Benutzerhandbuch
10-18 Vol. 3
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
32-bit register. Similarly executing the WRMSR instruction with the APIC register
address in ECX, writes bits 0 to 31 of register EAX to bits 0 to 31 of the specified APIC
register. If the register is a 64-bit register then bits 0 to 31 of register EDX are written
to bits 32 to 63 of the APIC register. The Interrupt Command Register is the only APIC
register that is implemented as a 64-bit MSR. The semantics of handling reserved
bits are defined in
address in ECX, writes bits 0 to 31 of register EAX to bits 0 to 31 of the specified APIC
register. If the register is a 64-bit register then bits 0 to 31 of register EDX are written
to bits 32 to 63 of the APIC register. The Interrupt Command Register is the only APIC
register that is implemented as a 64-bit MSR. The semantics of handling reserved
bits are defined in
.
10.5.1.2 APIC Register Address Space
The MSR address range between 0000_0800H through 0000_0BFFH is architectur-
ally reserved and dedicated for accessing APIC registers in x2APIC mode.
ally reserved and dedicated for accessing APIC registers in x2APIC mode.
provides the detailed list of the APIC registers in xAPIC mode and x2APIC mode. The
MSR address offset specified in the table is relative to the base MSR address of 800H.
The MMIO offset specified in the table is relative to the default base address of
FEE00000H.
There is a one-to-one mapping between the legacy xAPIC register MMIO offset and
the MSR address offset with the following exceptions:
MSR address offset specified in the table is relative to the base MSR address of 800H.
The MMIO offset specified in the table is relative to the default base address of
FEE00000H.
There is a one-to-one mapping between the legacy xAPIC register MMIO offset and
the MSR address offset with the following exceptions:
•
The Interrupt Command Register (ICR): The two 32-bit ICR registers in xAPIC
mode are merged into a single 64-bit MSR in x2APIC mode.
mode are merged into a single 64-bit MSR in x2APIC mode.
•
The Destination Format Register (DFR) is not supported in x2APIC mode.
•
The SELF IPI register is available only if x2APIC mode is enabled.
The MSR address space is compressed to allow for future growth. Every 32 bit
register on a 128- bit boundary in the legacy MMIO space is mapped to a single MSR
in the local x2APIC MSR address space. The upper 32-bits of all x2APIC MSRs (except
for the ICR) are reserved.
register on a 128- bit boundary in the legacy MMIO space is mapped to a single MSR
in the local x2APIC MSR address space. The upper 32-bits of all x2APIC MSRs (except
for the ICR) are reserved.
Table 10-3. Local APIC Register Address Map Supported by x2APIC
MMIO Offset
(xAPIC mode)
MSR Offset
(x2APIC
mode)
Register Name
R/W
Semantics
Comments
0000H-
0010H
000H-001H
Reserved
0020H
002H
Local APIC ID Register
Read only
See
for initial values.
0030H
003H
Local APIC Version
Register
Read only.
Same version between
extended and legacy
modes. Bit 24 is available
only to an x2APIC unit (in
xAPIC mode and x2APIC
modes, See Section
0040H-
0070H
004H-007H
Reserved