Intel 253668-032US Benutzerhandbuch
11-32 Vol. 3
MEMORY CACHE CONTROL
11.11.1 MTRR Feature Identification
The availability of the MTRR feature is model-specific. Software can determine if
MTRRs are supported on a processor by executing the CPUID instruction and reading
the state of the MTRR flag (bit 12) in the feature information register (EDX).
If the MTRR flag is set (indicating that the processor implements MTRRs), additional
information about MTRRs can be obtained from the 64-bit IA32_MTRRCAP MSR
(named MTRRcap MSR for the P6 family processors). The IA32_MTRRCAP MSR is a
read-only MSR that can be read with the RDMSR instruction. Figure 11-5 shows the
contents of the IA32_MTRRCAP MSR. The functions of the flags and field in this
register are as follows:
MTRRs are supported on a processor by executing the CPUID instruction and reading
the state of the MTRR flag (bit 12) in the feature information register (EDX).
If the MTRR flag is set (indicating that the processor implements MTRRs), additional
information about MTRRs can be obtained from the 64-bit IA32_MTRRCAP MSR
(named MTRRcap MSR for the P6 family processors). The IA32_MTRRCAP MSR is a
read-only MSR that can be read with the RDMSR instruction. Figure 11-5 shows the
contents of the IA32_MTRRCAP MSR. The functions of the flags and field in this
register are as follows:
•
VCNT (variable range registers count) field, bits 0 through 7 — Indicates
the number of variable ranges implemented on the processor.
the number of variable ranges implemented on the processor.
•
FIX (fixed range registers supported) flag, bit 8 — Fixed range MTRRs
(IA32_MTRR_FIX64K_00000 through IA32_MTRR_FIX4K_0F8000) are
supported when set; no fixed range registers are supported when clear.
(IA32_MTRR_FIX64K_00000 through IA32_MTRR_FIX4K_0F8000) are
supported when set; no fixed range registers are supported when clear.
•
WC (write combining) flag, bit 10 — The write-combining (WC) memory type
is supported when set; the WC type is not supported when clear.
is supported when set; the WC type is not supported when clear.
•
SMRR (System-Management Range Register) flag, bit 11 — The system-
management range register (SMRR) interface is supported when bit 11 is set; the
SMRR interface is not supported when clear.
management range register (SMRR) interface is supported when bit 11 is set; the
SMRR interface is not supported when clear.
Bit 9 and bits 11 through 63 in the IA32_MTRRCAP MSR are reserved. If software
attempts to write to the IA32_MTRRCAP MSR, a general-protection exception (#GP)
is generated.
Software must read IA32_MTRRCAP VCNT field to determine the number of variable
MTRRs and query other feature bits in IA32_MTRRCAP to determine additional capa-
bilities that are supported in a processor. For example, some processors may report
a value of ‘8’ in the VCNT field, other processors may report VCNT with different
values.
attempts to write to the IA32_MTRRCAP MSR, a general-protection exception (#GP)
is generated.
Software must read IA32_MTRRCAP VCNT field to determine the number of variable
MTRRs and query other feature bits in IA32_MTRRCAP to determine additional capa-
bilities that are supported in a processor. For example, some processors may report
a value of ‘8’ in the VCNT field, other processors may report VCNT with different
values.
Figure 11-5. IA32_MTRRCAP Register
VCNT — Number of variable range registers
FIX — Fixed range registers supported
WC — Write-combining memory type supported
63
0
Reserved
W
C
7
10
11
VCNT
F
I
X
8
9
Reserved
SMRR — SMRR interface supported