Intel 253668-032US Benutzerhandbuch
11-52 Vol. 3
MEMORY CACHE CONTROL
11.12.5 PAT Compatibility with Earlier IA-32 Processors
For IA-32 processors that support the PAT, the IA32_PAT MSR is always active. That
is, the PCD and PWT bits in page-table entries and in page-directory entries (that
point to pages) are always select a memory type for a page indirectly by selecting an
entry in the PAT. They never select the memory type for a page directly as they do in
earlier IA-32 processors that do not implement the PAT (see Table 11-6).
To allow compatibility for code written to run on earlier IA-32 processor that do not
support the PAT, the PAT mechanism has been designed to allow backward compati-
bility to earlier processors. This compatibility is provided through the ordering of the
PAT, PCD, and PWT bits in the 3-bit PAT entry index. For processors that do not imple-
ment the PAT, the PAT index bit (bit 7 in the page-table entries and bit 12 in the page-
directory entries) is reserved and set to 0. With the PAT bit reserved, only the first
four entries of the PAT can be selected with the PCD and PWT bits. At power-up or
reset (see Table 11-12), these first four entries are encoded to select the same
memory types as the PCD and PWT bits would normally select directly in an IA-32
processor that does not implement the PAT. So, if encodings of the first four entries
in the PAT are left unchanged following a power-up or reset, code written to run on
earlier IA-32 processors that do not implement the PAT will run correctly on IA-32
processors that do implement the PAT.
is, the PCD and PWT bits in page-table entries and in page-directory entries (that
point to pages) are always select a memory type for a page indirectly by selecting an
entry in the PAT. They never select the memory type for a page directly as they do in
earlier IA-32 processors that do not implement the PAT (see Table 11-6).
To allow compatibility for code written to run on earlier IA-32 processor that do not
support the PAT, the PAT mechanism has been designed to allow backward compati-
bility to earlier processors. This compatibility is provided through the ordering of the
PAT, PCD, and PWT bits in the 3-bit PAT entry index. For processors that do not imple-
ment the PAT, the PAT index bit (bit 7 in the page-table entries and bit 12 in the page-
directory entries) is reserved and set to 0. With the PAT bit reserved, only the first
four entries of the PAT can be selected with the PCD and PWT bits. At power-up or
reset (see Table 11-12), these first four entries are encoded to select the same
memory types as the PCD and PWT bits would normally select directly in an IA-32
processor that does not implement the PAT. So, if encodings of the first four entries
in the PAT are left unchanged following a power-up or reset, code written to run on
earlier IA-32 processors that do not implement the PAT will run correctly on IA-32
processors that do implement the PAT.