Intel 253668-032US Benutzerhandbuch
14-2 Vol. 3
POWER AND THERMAL MANAGEMENT
tools can access model-specific events and report the occurrences of state
transitions.
transitions.
14.2
P-STATE HARDWARE COORDINATION
The Advanced Configuration and Power Interface (ACPI) defines performance states
(P-state) that are used facilitate system software’s ability to manage processor
power consumption. Different P-state correspond to different performance levels
that are applied while the processor is actively executing instructions. Enhanced Intel
SpeedStep Technology supports P-state by providing software interfaces that control
the operating frequency and voltage of a processor.
With multiple processor cores residing in the same physical package, hardware
dependencies may exist for a subset of logical processors on a platform. These
dependencies may impose requirements that impact coordination of P-state transi-
tions. As a result, multi-core processors may require an OS to provide additional soft-
ware support for coordinating P-state transitions for those subsets of logical
processors.
A BIOS (following ACPI 3.0 specification) can choose to expose P-state as dependent
and hardware-coordinated to OS power management (OSPM) policy. To support
OSPMs, multi-core processors must have additional built-in support for P-state hard-
ware coordination and feedback.
Intel 64 and IA-32 processors with dependent P-state amongst a subset of logical
processors permit hardware coordination of P-state and provide a hardware-coordi-
nation feedback mechanism using IA32_MPERF MSR and IA32_APERF MSR. See
Figure 14-1 for an overview of the two 64-bit MSRs and the bullets below for a
detailed description:
(P-state) that are used facilitate system software’s ability to manage processor
power consumption. Different P-state correspond to different performance levels
that are applied while the processor is actively executing instructions. Enhanced Intel
SpeedStep Technology supports P-state by providing software interfaces that control
the operating frequency and voltage of a processor.
With multiple processor cores residing in the same physical package, hardware
dependencies may exist for a subset of logical processors on a platform. These
dependencies may impose requirements that impact coordination of P-state transi-
tions. As a result, multi-core processors may require an OS to provide additional soft-
ware support for coordinating P-state transitions for those subsets of logical
processors.
A BIOS (following ACPI 3.0 specification) can choose to expose P-state as dependent
and hardware-coordinated to OS power management (OSPM) policy. To support
OSPMs, multi-core processors must have additional built-in support for P-state hard-
ware coordination and feedback.
Intel 64 and IA-32 processors with dependent P-state amongst a subset of logical
processors permit hardware coordination of P-state and provide a hardware-coordi-
nation feedback mechanism using IA32_MPERF MSR and IA32_APERF MSR. See
Figure 14-1 for an overview of the two 64-bit MSRs and the bullets below for a
detailed description:
•
Use CPUID to check the P-State hardware coordination feedback capability bit.
CPUID.06H.ECX[Bit 0] = 1 indicates IA32_MPERF MSR and IA32_APERF MSR are
present.
CPUID.06H.ECX[Bit 0] = 1 indicates IA32_MPERF MSR and IA32_APERF MSR are
present.
•
IA32_MPERF MSR (0xE7) increments in proportion to a fixed frequency, which is
configured when the processor is booted.
configured when the processor is booted.
Figure 14-1. IA32_MPERF MSR and IA32_APERF MSR for P-state Coordination
63
0
IA32_MPERF (Addr: E7H)
63
0
IA32_APERF (Addr: E8H)