Intel 253668-032US Benutzerhandbuch
14-6 Vol. 3
POWER AND THERMAL MANAGEMENT
to the OS, it may be undesirable to allow the possibility of the processor delivering
increased performance that cannot be sustained after the calibration phase.
System software can temporarily disengage opportunistic processor performance
operation by setting bit 32 of the IA32_PERF_CTL MSR (0199H), using a read-
modify-write sequence on the MSR. The opportunistic processor performance opera-
tion can be re-engaged by clearing bit 32 in IA32_PERF_CTL MSR, using a read-
modify-write sequence. The DISENAGE bit in IA32_PERF_CTL is not reflected in bit
32 of the IA32_PERF_STATUS MSR (0198H), and it is not shared between logical
processors in a physical package. In order for OS to engage IDA/Turbo mode, the
BIOS must
increased performance that cannot be sustained after the calibration phase.
System software can temporarily disengage opportunistic processor performance
operation by setting bit 32 of the IA32_PERF_CTL MSR (0199H), using a read-
modify-write sequence on the MSR. The opportunistic processor performance opera-
tion can be re-engaged by clearing bit 32 in IA32_PERF_CTL MSR, using a read-
modify-write sequence. The DISENAGE bit in IA32_PERF_CTL is not reflected in bit
32 of the IA32_PERF_STATUS MSR (0198H), and it is not shared between logical
processors in a physical package. In order for OS to engage IDA/Turbo mode, the
BIOS must
•
enable opportunistic processor performance operation, as described in Section
14.3.2.1,
14.3.2.1,
•
expose the operating points associated with IDA/Turbo mode to the OS.
14.3.2.3 Required Changes to OS Power Management P-state Policy
Intel Dynamic Acceleration (IDA) and Intel Turbo Boost Technology can provide
opportunistic performance greater than the performance level corresponding to the
maximum qualified frequency of the processor (see CPUID’s brand string informa-
tion). System software can use a pair of MSRs to observe performance feedback.
Software must query for the presence of IA32_APERF and IA32_MPERF (see Section
14.2). The ratio between IA32_APERF and IA32_MPERF is architecturally defined and
a value greater than unity indicates performance increase occurred during the obser-
vation period due to IDA. Without incorporating such performance feedback, the
target P-state evaluation algorithm can result in a non-optimal P-state target.
There are other scenarios under which OS power management may want to disable
IDA, some of these are listed below:
opportunistic performance greater than the performance level corresponding to the
maximum qualified frequency of the processor (see CPUID’s brand string informa-
tion). System software can use a pair of MSRs to observe performance feedback.
Software must query for the presence of IA32_APERF and IA32_MPERF (see Section
14.2). The ratio between IA32_APERF and IA32_MPERF is architecturally defined and
a value greater than unity indicates performance increase occurred during the obser-
vation period due to IDA. Without incorporating such performance feedback, the
target P-state evaluation algorithm can result in a non-optimal P-state target.
There are other scenarios under which OS power management may want to disable
IDA, some of these are listed below:
•
When engaging ACPI defined passive thermal management, it may be more
effective to disable IDA for the duration of passive thermal management.
effective to disable IDA for the duration of passive thermal management.
•
When the user has indicated a policy preference of power savings over perfor-
mance, OS power management may want to disable IDA while that policy is in
effect.
mance, OS power management may want to disable IDA while that policy is in
effect.
Figure 14-2. IA32_PERF_CTL Register
63
0
Reserved
16
EIST Transition Target
15
32
33
31
IDA/Turbo DISENGAGE