Intel 253668-032US Benutzerhandbuch
14-10 Vol. 3
POWER AND THERMAL MANAGEMENT
Reference, A-M,” of Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 2A).
If CPUID.05H.ECX[Bit 1] = 1, the target processor supports using interrupts as
break-events for MWAIT, even when interrupts are disabled. Use this feature to
measure C-state residency as follows:
Volume 2A).
If CPUID.05H.ECX[Bit 1] = 1, the target processor supports using interrupts as
break-events for MWAIT, even when interrupts are disabled. Use this feature to
measure C-state residency as follows:
•
Software can write to bit 0 in the MWAIT Extensions register (ECX) when issuing
an MWAIT to enter into a processor-specific C-state or sub C-state.
an MWAIT to enter into a processor-specific C-state or sub C-state.
•
When a processor comes out of an inactive C-state or sub C-state, software can
read a timestamp before an interrupt service routine (ISR) is potentially
executed.
read a timestamp before an interrupt service routine (ISR) is potentially
executed.
CPUID.05H.EDX allows software to enumerate processor-specific C-states and sub
C-states available for use with MWAIT extensions. IA-32 processors may support
more than one C-state of a given C-state type. These are called sub C-states. Numer-
ically higher C-state have higher power savings and latency (upon entering and
exiting) than lower-numbered C-state.
At CPL = 0, system software can specify desired C-state and sub C-state by using the
MWAIT hints register (EAX). Processors will not go to C-state and sub C-state deeper
than what is specified by the hint register. If CPL > 0 and if MONITOR/MWAIT is
supported at CPL > 0, the processor will only enter C1-state (regardless of the
C-state request in the hints register).
Executing MWAIT generates an exception on processors operating at a privilege level
where MONITOR/MWAIT are not supported.
C-states available for use with MWAIT extensions. IA-32 processors may support
more than one C-state of a given C-state type. These are called sub C-states. Numer-
ically higher C-state have higher power savings and latency (upon entering and
exiting) than lower-numbered C-state.
At CPL = 0, system software can specify desired C-state and sub C-state by using the
MWAIT hints register (EAX). Processors will not go to C-state and sub C-state deeper
than what is specified by the hint register. If CPL > 0 and if MONITOR/MWAIT is
supported at CPL > 0, the processor will only enter C1-state (regardless of the
C-state request in the hints register).
Executing MWAIT generates an exception on processors operating at a privilege level
where MONITOR/MWAIT are not supported.
NOTE
If MWAIT is used to enter a C-state (including sub C-state) that is
numerically higher than C1, a store to the address range armed by
MONITOR instruction will cause the processor to exit MWAIT if the
store was originated by other processor agents. A store from non-
processor agent may not cause the processor to exit MWAIT.
numerically higher than C1, a store to the address range armed by
MONITOR instruction will cause the processor to exit MWAIT if the
store was originated by other processor agents. A store from non-
processor agent may not cause the processor to exit MWAIT.
14.5
THERMAL MONITORING AND PROTECTION
The IA-32 architecture provides the following mechanisms for monitoring tempera-
ture and controlling thermal power:
1. The catastrophic shutdown detector forces processor execution to stop if the
ture and controlling thermal power:
1. The catastrophic shutdown detector forces processor execution to stop if the
processor’s core temperature rises above a preset limit.
2. Automatic and adaptive thermal monitoring mechanisms force the
processor to reduce it’s power consumption in order to operate within predeter-
mined temperature limits.
mined temperature limits.
3. The software controlled clock modulation mechanism permits operating
systems to implement power management policies that reduce power