Intel 253668-032US Benutzerhandbuch
14-14 Vol. 3
POWER AND THERMAL MANAGEMENT
14.5.2.4 Performance State Transitions and Thermal Monitoring
If the thermal control circuitry (TCC) for thermal monitor (TM1/TM2) is active, writes
to the IA32_PERF_CTL will effect a new target operating point as follows:
to the IA32_PERF_CTL will effect a new target operating point as follows:
•
If TM1 is enabled and the TCC is engaged, the performance state transition can
commence before the TCC is disengaged.
commence before the TCC is disengaged.
•
If TM2 is enabled and the TCC is engaged, the performance state transition
specified by a write to the IA32_PERF_CTL will commence after the TCC has
disengaged.
specified by a write to the IA32_PERF_CTL will commence after the TCC has
disengaged.
14.5.2.5 Thermal Status Information
The status of the temperature sensor that triggers the thermal monitor (TM1/TM2) is
indicated through the thermal status flag and thermal status log flag in the
IA32_THERM_STATUS MSR (see Figure 14-8).
The functions of these flags are:
indicated through the thermal status flag and thermal status log flag in the
IA32_THERM_STATUS MSR (see Figure 14-8).
The functions of these flags are:
•
Thermal Status flag, bit 0 — When set, indicates that the processor core
temperature is currently at the trip temperature of the thermal monitor and that
the processor power consumption is being reduced via either TM1 or TM2,
depending on which is enabled. When clear, the flag indicates that the core
temperature is below the thermal monitor trip temperature. This flag is read only.
temperature is currently at the trip temperature of the thermal monitor and that
the processor power consumption is being reduced via either TM1 or TM2,
depending on which is enabled. When clear, the flag indicates that the core
temperature is below the thermal monitor trip temperature. This flag is read only.
•
Thermal Status Log flag, bit 1 — When set, indicates that the thermal sensor
has tripped since the last power-up or reset or since the last time that software
cleared this flag. This flag is a sticky bit; once set it remains set until cleared by
software or until a power-up or reset of the processor. The default state is clear.
has tripped since the last power-up or reset or since the last time that software
cleared this flag. This flag is a sticky bit; once set it remains set until cleared by
software or until a power-up or reset of the processor. The default state is clear.
Figure 14-7. MSR_THERM2_CTL Register for Supporting TM2
63
0
Reserved
15
TM2 Transition Target