Intel 253668-032US Benutzerhandbuch
14-18 Vol. 3
POWER AND THERMAL MANAGEMENT
clock modulation at the duty cycle specified by TM1 takes precedence, regardless of
the setting of the on-demand clock modulation duty cycle.
For Hyper-Threading Technology enabled processors, the
IA32_CLOCK_MODULATION register is duplicated for each logical processor. In order
for the On-demand clock modulation feature to work properly, the feature must be
enabled on all the logical processors within a physical processor. If the programmed
duty cycle is not identical for all the logical processors, the processor clock will modu-
late to the highest duty cycle programmed.
For the P6 family processors, on-demand clock modulation was implemented
through the chipset, which controlled clock modulation through the processor’s
STPCLK# pin.
the setting of the on-demand clock modulation duty cycle.
For Hyper-Threading Technology enabled processors, the
IA32_CLOCK_MODULATION register is duplicated for each logical processor. In order
for the On-demand clock modulation feature to work properly, the feature must be
enabled on all the logical processors within a physical processor. If the programmed
duty cycle is not identical for all the logical processors, the processor clock will modu-
late to the highest duty cycle programmed.
For the P6 family processors, on-demand clock modulation was implemented
through the chipset, which controlled clock modulation through the processor’s
STPCLK# pin.
14.5.4
Detection of Thermal Monitor and Software Controlled
Clock Modulation Facilities
The ACPI flag (bit 22) of the CPUID feature flags indicates the presence of the
IA32_THERM_STATUS, IA32_THERM_INTERRUPT, IA32_CLOCK_MODULATION
MSRs, and the xAPIC thermal LVT entry.
The TM1 flag (bit 29) of the CPUID feature flags indicates the presence of the auto-
matic thermal monitoring facilities that modulate clock duty cycles.
IA32_THERM_STATUS, IA32_THERM_INTERRUPT, IA32_CLOCK_MODULATION
MSRs, and the xAPIC thermal LVT entry.
The TM1 flag (bit 29) of the CPUID feature flags indicates the presence of the auto-
matic thermal monitoring facilities that modulate clock duty cycles.
14.5.5
On Die Digital Thermal Sensors
On die digital thermal sensor can be read using an MSR (no I/O interface). In Intel
Core Duo processors, each core has a unique digital sensor whose temperature is
accessible using an MSR. The digital thermal sensor is the preferred method for
reading the die temperature because (a) it is located closer to the hottest portions of
the die, (b) it enables software to accurately track the die temperature and the
potential activation of thermal throttling.
Core Duo processors, each core has a unique digital sensor whose temperature is
accessible using an MSR. The digital thermal sensor is the preferred method for
reading the die temperature because (a) it is located closer to the hottest portions of
the die, (b) it enables software to accurately track the die temperature and the
potential activation of thermal throttling.
14.5.5.1 Digital Thermal Sensor Enumeration
The processor supports a digital thermal sensor if CPUID.06H.EAX[0] = 1. If the
processor supports digital thermal sensor, EBX[bits 3:0] determine the number of
thermal thresholds that are available for use.
Software sets thermal thresholds by using the IA32_THERM_INTERRUPT MSR. Soft-
ware reads output of the digital thermal sensor using the IA32_THERM_STATUS
MSR.
processor supports digital thermal sensor, EBX[bits 3:0] determine the number of
thermal thresholds that are available for use.
Software sets thermal thresholds by using the IA32_THERM_INTERRUPT MSR. Soft-
ware reads output of the digital thermal sensor using the IA32_THERM_STATUS
MSR.