Intel 253668-032US Benutzerhandbuch

15-2   Vol. 3

MACHINE-CHECK ARCHITECTURE

15.2 COMPATIBILITY 

WITH 

PENTIUM

PROCESSOR

The Pentium 4, Intel Xeon, and P6 family processors support and extend the 

machine-check exception mechanism introduced in the Pentium processor. 

The Pentium processor reports the following machine-check errors:

•

data parity errors during read cycles

•

unsuccessful completion of a bus cycle

The above errors are reported using the P5_MC_TYPE and P5_MC_ADDR 

MSRs (implementation specific for the Pentium processor). Use the RDMSR 

instruction to read these MSRs. See Appendix B, “Model-Specific Registers 

(MSRs),” for the addresses.
The machine-check error reporting mechanism that Pentium processors use 

is similar to that used in Pentium 4, Intel Xeon, and P6 family processors. 

When an error is detected, it is recorded in P5_MC_TYPE and P5_MC_ADDR; 

the processor then generates a machine-check exception (#MC).
See Section 15.3.3, “Mapping of the Pentium

Errors to the Machine-Check Architecture,” and Section 15.10.2, “Pentium

Processor Machine-Check Exception Handling,” for information on compati-

bility between machine-check code written to run on the Pentium processors 

and code written to run on P6 family processors.

15.3 MACHINE-CHECK 

MSRS

Machine check MSRs in the Pentium 4, Intel Xeon, and P6 family processors 

consist of a set of global control and status registers and several error-

reporting register banks. See Figure 15-1.