Intel 253668-032US Benutzerhandbuch
15-6 Vol. 3
MACHINE-CHECK ARCHITECTURE
15.3.1.3 IA32_MCG_CTL MSR
The IA32_MCG_CTL MSR is present if the capability flag MCG_CTL_P is set in
the IA32_MCG_CAP MSR.
IA32_MCG_CTL controls the reporting of machine-check exceptions. If
IA32_MCG_CTL controls the reporting of machine-check exceptions. If
present, writing 1s to this register enables machine-check features and
writing all 0s disables machine-check features. All other values are unde-
fined and/or implementation specific.
15.3.2
Error-Reporting Register Banks
Each error-reporting register bank can contain the IA32_MCi_CTL,
IA32_MCi_STATUS, IA32_MCi_ADDR, and IA32_MCi_MISC MSRs. The
number of reporting banks is indicated by bits [7:0] of IA32_MCG_CAP MSR
(address 0179H). The first error-reporting register (IA32_MC0_CTL) always
starts at address 400H.
See Appendix B, “Model-Specific Registers (MSRs),” for addresses of the
See Appendix B, “Model-Specific Registers (MSRs),” for addresses of the
error-reporting registers in the Pentium 4 and Intel Xeon processors; and for
addresses of the error-reporting registers P6 family processors.
15.3.2.1 IA32_MC
i
_CTL MSRs
The IA32_MCi_CTL MSR controls error reporting for errors produced by a
particular hardware unit (or group of hardware units). Each of the 64 flags
(EEj) represents a potential error. Setting an EEj flag enables reporting of
the associated error and clearing it disables reporting of the error. The
processor does not write changes to bits that are not implemented.
Figure 15-4 shows the bit fields of IA32_MCi_CTL.
NOTE
For P6 family processors, processors based on Intel Core microarchi-
tecture (excluding processors with
tecture (excluding processors with
DisplayFamily_DisplayModel
Figure 15-4. IA32_MCi_CTL Register
EEj—Error reporting enable flag
63
0
1
2
3
E
E
E
0
1
1
E
E
E
0
2
2
E
E
E
0
0
0
E
E
E
6
1
1
E
E
E
6
2
2
E
E
E
6
3
3
62 61
. . . . .
(where j is 00 through 63)