Intel 253668-032US Benutzerhandbuch

Vol. 3   15-19

MACHINE-CHECK ARCHITECTURE

beyond those of threshold-based error reporting (Section 15.4). With 

threshold-based error reporting, software is limited to use periodic polling to 

query the status of hardware corrected MC errors. CMCI provides a signaling 

mechanism to deliver a local interrupt based on threshold values that soft-

ware can program using the IA32_MCi_CTL2 MSRs. 
CMCI is disabled by default. System software is required to enable CMCI for 

each IA32_MCi bank that support the reporting of hardware corrected errors 

if IA32_MCG_CAP[10] = 1.
System software use IA32_MCi_CTL2 MSR to enable/disable the CMCI capa-

bility for each bank and program threshold values into IA32_MCi_CTL2 MSR. 

CMCI is not affected by the CR4.MCE bit, and it is not affected by the 

IA32_MCi_CTL MSR’s.
To detect the existence of thresholding for a given bank, software writes only 

bits 14:0 with the threshold value. If the bits persist, then thresholding is 

available (and CMCI is available). If the bits are all 0's, then no thresholding 

exists. To detect that CMCI signaling exists, software writes a 1 to bit 30 of 

the MCi_CTL2 register. Upon subsequent read, If Bit 30 = 0, no CMCI is 

available for this bank. If Bit 30 = 1, then CMCI is available and enabled.

15.5.1 

CMCI Local APIC Interface

The interaction of CMCI is depicted in Figure 15-9. 

Figure 15-9.  CMCI Behavior

Error threshold

63

0

MCi_CTL2

30

31

Error count

53

0

29

14

37

MCi_STATUS

38

52

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